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BEGIN:VEVENT
DTSTAMP:20260730T152640Z
LOCATION:Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20260728T172800
DTEND;TZID=America/Los_Angeles:20260728T172800
UID:dac_DAC 2026_sess306_WIP3209@linklings.com
SUMMARY:Late Breaking Results: Fast Energy-Aware Neural Network Modeling f
 or Efficient FPGA-Based Inference
DESCRIPTION:Rishi Agrawal (BITS Pilani, Hyderabad Campus) and Andrea Guerr
 ieri (EPFL and HES-SO)\n\nFPGAs provide customizable hardware acceleration
  that enables efficient, low-latency execution of machine learning inferen
 ce through application-specific parallelism. While resource utilization an
 d latency can typically be estimated early in the design process, accurate
  power consumption analysis generally requires completing the full hardwar
 e design flow, which may take several hours. In this paper, we present a f
 ramework that rapidly identifies high-quality, energy-efficient FPGA desig
 ns without requiring full compilation. The proposed approach converges to 
 an optimal design point within seconds, achieving up to a 1000$\times$ spe
 edup compared to conventional methods.\n\nTrack: Student\n\n
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