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DTSTAMP:20260730T152640Z
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UID:dac_DAC 2026_sess306_WIP3208@linklings.com
SUMMARY:Late Breaking Results: Synthesizable 8-Bit Digital Memristor Emula
 tor with Programmable State Retention for Accelerated Edge Computing
DESCRIPTION:Shekhar Suman Borah and Philip Waldecker (Center for Robotics 
 and Intelligent Systems, The University of Texas at Tyler, Tyler, Texas, U
 SA); Henry Torbert (National Soil Dynamics Lab, USDA-ARS); and Prabha Sund
 aravadivel (Associate Professor, The University of Texas at Tyler)\n\nMemr
 istive devices are promising for neuromorphic and in-memory computing, but
  practical analog implementations often face variability and fabrication c
 hallenges. This work presents a synthesizable 8-bit digital memristor emul
 ator implemented in Verilog and targeted for FPGA realization. The design 
 employs a discrete-time, threshold-based state update mechanism with Q1.15
  fixed-point arithmetic at 10~kHz sampling. Simulation results demonstrate
  frequency-dependent pinched hysteresis consistent with memristive behavio
 r, as well as programmable SET/RESET resistance modulation and stable non-
 volatile retention under zero excitation. The bounded 8-bit state ensures 
 deterministic operation suitable for hardware deployment. The proposed arc
 hitecture provides a compact and reproducible digital platform for archite
 ctural exploration of memristor-inspired computing systems, with scalabili
 ty toward FPGA-based arrays for neuromorphic and edge computing applicatio
 ns.\n\nTrack: Student\n\n
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