BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20260730T152640Z
LOCATION:Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20260728T171100
DTEND;TZID=America/Los_Angeles:20260728T171100
UID:dac_DAC 2026_sess306_WIP3187@linklings.com
SUMMARY:Late Breaking Results: Die Area and Temperature Co-Optimization fo
 r Thermal Throttling Mitigation in Mobile Application Processors
DESCRIPTION:Jisoo Hwang (Sungkyunkwan University, Samsung Electronics) and
  SoYoung Kim (Sungkyunkwan University)\n\nTo mitigate workload-driven ther
 mal throttling, advanced mobile packages adopt heat escape structures, whi
 ch can bias the memory interface to one die side and significantly tighten
  the trade-off between thermally-constrained performance and interconnect 
 length. We formulate thermal throttling-aware floorplanning that jointly o
 ptimizes die area, peak temperature, and xPU-to-memory-interface wirelengt
 h under such structure-induced asymmetry. We construct Pareto fronts via s
 patio-thermal co-exploration and extract a knee point to produce an action
 able budgeting rule: a modest +10% area margin yields a −6.7°C peak temper
 ature reduction with only +4.7% wirelength overhead, effectively guiding e
 arly-stage floorplanning.\n\nTrack: Student\n\n
END:VEVENT
END:VCALENDAR