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DTSTAMP:20260730T152640Z
LOCATION:Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20260728T172700
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UID:dac_DAC 2026_sess306_WIP3171@linklings.com
SUMMARY:Late Breaking Results: Analog Circuit Sizing Optimization using Pr
 ocrustes-Guided Machine Learning Heuristics
DESCRIPTION:Brandon Hippe and David Burnett (Villanova University) and Lyd
 ia Lee (Sandia National Laboratories)\n\nAutomated chip design techniques 
 are commonplace in digital IC design. Hardware description languages and r
 egister-transfer logic (RTL) code allow a design to be abstracted beyond a
  specific process. However, analog circuit performance is inherently tied 
 to the specific technology and tradeoffs made during the design process. D
 evelopments in machine and reinforcement learning show promise for automat
 ing the analog design process, though these algorithms require an objectiv
 e function to optimize. In this work, we demonstrate the use of Procrustes
  distance as an analog circuit sizing heuristic suitable for machine learn
 ing optimization,\nsizing an actively-loaded differential amplifier with a
  constant-gm bias circuit in an open-source 130 nm process, achieving over
  60% increase in unity gain frequency over a manually-sized benchmark.\n\n
 Track: Student\n\n
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