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DTSTAMP:20260730T152639Z
LOCATION:Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20260728T170500
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UID:dac_DAC 2026_sess306_WIP3157@linklings.com
SUMMARY:Split–and–Sync Bayesian Learning–Driven SRAM Compiler: Automatic D
 esign Tuning with Optimal Banking
DESCRIPTION:Jaeseung Baik (Kwangwoon University, Republic of Korea); Ijun 
 Jang (Kwangwoon University); Gwanwoo Park (Kwangwoon University, Republic 
 of Korea); Sejun Park and Mingeun Song (Yonsei University, Republic of Kor
 ea); Dahun Ko (Yonsei university); Doohyun Yu (Yonsei University, Republic
  of Korea); and Hanwool Jeong (Yonsei University)\n\nWe propose a Split-an
 d-Sync Bayesian learning framework for SRAM compiler optimization under ma
 cro-level timing and power constraints. The framework decomposes these glo
 bal constraints into leaf-cell-level objectives, where each leaf cell—such
  as a controller, decoder, or peripheral unit—is locally optimized through
  constraint-aware tuning. Our flow directly adjusts transistor-level param
 eters—widths and threshold voltages—and automatically regenerates the sche
 matic and layout for each candidate. A bank-adaptive search jointly explor
 es single- and multi-bank organizations, overcoming fixed banking rules. I
 mplemented in a 28nm SRAM compiler, the method achieves 6.87%-15.8% in dyn
 amic power reduction, 25.07%-26.45% access speed improvement, and a 4.5× r
 eduction in total optimization cost.\n\nTrack: Student\n\n
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