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DTSTAMP:20260730T152640Z
LOCATION:Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20260728T172700
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UID:dac_DAC 2026_sess306_WIP3152@linklings.com
SUMMARY:Hierarchical Learning–Based Digital Circuit Design Tuning Framewor
 k for Power-Delay Optimization
DESCRIPTION:Ijun Jang (Kwangwoon University); Jaeseung Baik and Gwanwoo Pa
 rk (Kwangwoon University, Republic of Korea); Sejun Park and Mingeun Song 
 (Yonsei University, Republic of Korea); Dahun Ko (Yonsei university); Dooh
 yun Yu (Yonsei University, Republic of Korea); and Hanwool Jeong (Yonsei U
 niversity)\n\nWe present a learning-based transistor-level design optimiza
 tion framework for digital logic circuits that fully regenerates schematic
 s and layouts after synthesis or place-and-route. Unlike conventional gate
 -level optimization limited to fixed standard-cell variants, it directly t
 unes transistor parameters. Bayesian learning with physics-guided regressi
 on refines delay and power characteristics, while a layout-in-the-loop eng
 ine ensures DRC-clean results through probabilistic search and geometric s
 ampling. To enable fast convergence, the framework adopts a hierarchical s
 tructure that synchronizes local optimizations with global updates. Across
  multiplier, divider, and adder-tree circuits, it achieves up to 12% dynam
 ic-power reduction and 5–10% delay improvement within 28–52 hours using fo
 ur-core parallelism.\n\nTrack: Student\n\n
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