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DTSTAMP:20260730T152639Z
LOCATION:Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20260728T170800
DTEND;TZID=America/Los_Angeles:20260728T170900
UID:dac_DAC 2026_sess306_WIP1707@linklings.com
SUMMARY:Linearly Scalable Algorithms for DFT Static Verification, Coverage
  Analysis, and Debug at RTL
DESCRIPTION:Kanad Chakraborty (Real Intent) and Vinod Viswanath (Real Inte
 nt, Inc.)\n\nIn this paper, we present DFT static verification and debug a
 s a powerful methodology that is scalable to designs with billions of gate
 s. The proposed methodology avoids the pitfalls of alternative approaches 
 such as simulation, formal verification, and language learning models (LLM
 s) and complements the design sign-off flow. We highlight four important D
 FT verification problems, viz., sequential depth, scan isolation, DFT conn
 ectivity checking, and early RTL fault coverage analysis. Each problem com
 es with different pitfalls in existing methodology which prevents arbitrar
 y scaling in design size. We present efficient and scalable static algorit
 hms that scale linearly with the size of the design graph (O(V+E) in the w
 orst case, where V is the number of gates/instances and E is the number of
  point-to-point nets connecting the instances). We also present results on
  large scale (100+ million gates) industrial designs from mobile SoC and A
 I/Edge application domains.\n\nTrack: Student\n\n
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