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DTSTAMP:20260730T152639Z
LOCATION:Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20260728T170400
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UID:dac_DAC 2026_sess306_WIP1627@linklings.com
SUMMARY:R5-Link : Enhancing RISC-V Multi-Core Efficiency with Hardware Mes
 sage Passing Channels in a 2D Mesh Network
DESCRIPTION:Yosef Ida, Nachman Abargil, Sarit Shvimer, Alex Grinshpun, and
  Freddy Gabbay (The Hebrew University)\n\nEfficient inter-core communicati
 on (ICC) is vital for performance and scalability in multi-core systems. W
 e present R5-Link (RISC-V Link), a hardware–software co-designed ICC mecha
 nism enabling low-latency, contention-free message passing across a 2D mes
 h network. Unlike traditional shared-memory or scratchpad-based methods, R
 5-Link uses dedicated bi-directional hardware queues and lightweight MPI-c
 ompatible APIs for direct neighbor-to-neighbor data exchange. This design 
 eliminates complex synchronization and memory contention, improving commun
 ication efficiency without interfering with core execution. Implemented on
  a PULP RISC-V SoC (16 nm FinFET), R5-Link achieves 6.6–14.8× lower latenc
 y and 6.6–41× higher throughput compared to software-based MPI communicati
 on.\n\nTrack: Student\n\n
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