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BEGIN:VEVENT
DTSTAMP:20260730T152639Z
LOCATION:Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20260728T170000
DTEND;TZID=America/Los_Angeles:20260728T170000
UID:dac_DAC 2026_sess306_WIP1002@linklings.com
SUMMARY:An Autonomous Design Agent of Parallel Feedforward Equalizer for A
 dvanced Wireline   Receivers
DESCRIPTION:You-Cheng Tu, Rui-Yong Kuo, and Wei-Zen Chen (NYCU)\n\nFeedfor
 ward equalizers (FFEs) are critical digital signal processing (DSP) compon
 ents in ultra-high speed wireline receivers, frequently limiting power and
  area efficiency while requiring extensive design effort. This work introd
 uces an autonomous design agent that automatically generates FFEs from sys
 tem specifications to Verilog implementation. The framework employs a comp
 utational data-flow graph model combining unfolding and fast FIR algorithm
 , along with nonlinear programming for architecture to circuit level optim
 ization. A 128-parallel, 24-tap FFE for a 112-Gbps PAM-4 receiver is succe
 ssfully synthesized in TSMC 28-nm CMOS within 6 hours using the design age
 nt, achieving 14 % power and 25 % area savings.\n\nTrack: Student\n\n
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