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DTSTAMP:20260730T152640Z
LOCATION:Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20260728T174000
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UID:dac_DAC 2026_sess306_LBR148@linklings.com
SUMMARY:Neural Subgraph Matching for Hardware Decompilation in Gate-Level 
 Netlists
DESCRIPTION:Yunzhen Liu (University of Massachusetts Amherst), Yingjie Li 
 (Simon Fraser University), and Nan Wu (George Washington University)\n\nMo
 dern IC globalization and automated synthesis often produce flattened netl
 ists that obscure design intent, complicating hardware security analysis a
 nd reverse engineering. Traditional decompilation methods based on exact s
 ubgraph isomorphism or fixed libraries are computationally expensive and s
 truggle to detect unseen logic patterns. We propose a self-supervised neur
 al subgraph matching framework that decomposes netlists into k-hop network
 s and embeds them into a latent order space to effectively identify repeat
 ed arithmetic primitives. Experiments on adders and multipliers show that 
 the method generalizes from small training circuits to larger designs, ena
 bling scalable recovery of high-level behavior from gate-level netlists.\n
 \nTrack: Student\n\n
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