BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20260730T152640Z
LOCATION:Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20260728T174200
DTEND;TZID=America/Los_Angeles:20260728T174200
UID:dac_DAC 2026_sess306_LBR130@linklings.com
SUMMARY:Late Breaking Results: HUSH: Silencing Inter-Core Interference in 
 Real-Time Cache Analysis
DESCRIPTION:Haoyuan Ren (University of science and technology of China); Y
 inkang Gao (Department of Computer Science and Technology, University of S
 cience and Technology of China); Yixuan Zhu, Bo Zhang, and teng wang (Univ
 ersity of Science and Technology of China); Wenqi Lou (USTC); and Xi Li (U
 niversity of Science and Technology of China)\n\nStatic worst-case executi
 on time (WCET) analysis for multicore real-time systems remains pessimisti
 c because write-invalidate coherence perturbs remote cache states at run t
 ime, preventing per-core hit/miss classification. We present HUSH, a write
 -update coherence that silences interference while bounding update traffic
  with time-based self-invalidation. The timeout defines a sharing window a
 nd is tuned offline to balance predictability and performance. On SPLASH-2
  in gem5, HUSH reduces worst-case total memory latency (WCML) by 30.7x and
  8.4x vs. PMSI and PENDULUM*, while keeping average performance within 1.1
 7x of MSI baseline.\n\nTrack: Student\n\n
END:VEVENT
END:VCALENDAR