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DTSTAMP:20260730T152640Z
LOCATION:Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20260728T173800
DTEND;TZID=America/Los_Angeles:20260728T173800
UID:dac_DAC 2026_sess306_LBR125@linklings.com
SUMMARY:DScNMP: A Dataflow Scheduling for  the Precision-Scalable Near-mem
 ory Processing Microarchitecture
DESCRIPTION:yueting Li (Hangzhou International Innovation Institute, Beiha
 ng University)\n\nNear-memory processing (NMP) mitigates the overhead of h
 ost-memory data movement while maintaining efficient data access.\nWe intr
 oduce DScNMP, an architecture-dataflow co-design that employs dataflow sch
 eduling to optimize NMP executions.\nDScNMP incorporates dynamic workload 
 scheduling, intra-cycle coordinated control, and state supervision units, 
 ensuring efficient resource management.\nEvaluation results show that DScN
 MP, occupies 0.006384 mm^2 in 14 nm, achieves 2.7× lower data access laten
 cy, up to 8.9× and 4.9× fewer cycles for external data movement and memory
 -bound workloads, respectively, and delivers 2.4× higher multiply-accumula
 te efficiency than Armv8.1-M.\n\nTrack: Student\n\n
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