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DTSTAMP:20260730T152640Z
LOCATION:Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20260728T173700
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UID:dac_DAC 2026_sess306_LBR119@linklings.com
SUMMARY:Late Breaking Results: LLM-Driven Constraint Generation and Deferr
 ed Shape Exploration for Analog IC Floorplanning
DESCRIPTION:Yu Chen and Fuxing Huang (Southeast University); Chengjie Liu 
 (Nanjing University); Xi Wang (Southeast University); and Ziran Zhu (Schoo
 l of Integrated Circuits, Southeast University)\n\nAnalog integrated circu
 it (IC) layout automation is fundamentally hindered by the semantic gap in
  constraint extraction and the premature binding of device shapes. Traditi
 onal serial flows rely on simplistic, netlist driven constraint handling a
 nd decouple device generation from floorplanning. This rigidity drasticall
 y restricts the feasible solution space, often leading to severe dead-spac
 e overhead and performance degradation. To address these bottlenecks, we p
 ropose CoLLM-DDM, a novel analog layout automation framework. It synergize
 s a Constraint-aware Large Language Model (CoLLM) engine, which intelligen
 tly extracts comprehensive topological and signal-flow constraints from bo
 th schematics and netlists, with a Deferred Decision Making (DDM) based fl
 oorplanning algorithm. By dynamically exploring full-spectrum device foldi
 ng schemes and deferring geometric binding to the global placement phase, 
 CoLLM-DDM maximally preserves optimization freedom. Experimental results o
 n industrial grade analog circuits demonstrate that, compared to the state
 -of-the-art framework, CoLLM-DDM achieves a 63% reduction in dead space an
 d a 7% improvement in core net half-perimeter wirelength (HPWL), all while
  maintaining a sub-1.5-second runtime.\n\nTrack: Student\n\n
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