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DTSTAMP:20260730T152640Z
LOCATION:Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20260728T174400
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UID:dac_DAC 2026_sess306_LBR107@linklings.com
SUMMARY:Late Breaking Results: A Coarse-to-Fine PCB Placement Framework vi
 a LLM-Guided Component Grouping and Group-Aware Placement
DESCRIPTION:Junhong Li, Keyu Peng, Fuxing Huang, and Hao Wu (Southeast Uni
 versity) and Ziran Zhu (School of Integrated Circuits, Southeast Universit
 y)\n\nThis paper introduces a coarse-to-fine printed circuit board (PCB) p
 lacement framework bridging high-level functional design intent and physic
 al implementation. First, a large language model (LLM)-guided component gr
 ouping engine utilizes multi-modal feature serialization, topology-enriche
 d retrieval-augmented generation (RAG), and multi-agent reasoning to captu
 re functional constraints missed by standard netlists. Subsequently, a gro
 up-aware placement phase employs a hierarchical initial placement strategy
  via B*-tree packing to physically realize these modules. This prevents th
 e pitfalls of blind initialization, providing an optimal starting point fo
 r group-aware global placement and constraint graph-based mixed integer li
 near programming (MILP) legalization. Experimental results demonstrate tha
 t the proposed framework significantly surpasses advanced placers in post-
 routing quality.\n\nTrack: Student\n\n
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