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DTSTAMP:20260730T152640Z
LOCATION:Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20260728T174700
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UID:dac_DAC 2026_sess306_LBR098@linklings.com
SUMMARY:Late Breaking Results: Towards Low-Latency TinyML via Regularized 
 Activation Packing
DESCRIPTION:Georgios Mentzos (Karlsruhe Institute of Technology), Konstant
 inos Balaskas (University of Patras), Georgios Zervakis (National Technica
 l University of Athens), and Joerg Henkel (KIT)\n\nIn recent years, custom
 ized and low-precision CNNs have emerged,\ntailored for TinyML application
 s and well-suited for FPGA deploy-\nment. DSP Packing has been proposed to
  increase the computa-\ntional density of the limited DSP blocks on modern
  FPGAs, but\ncurrent solutions under-utilize key DSP components, like the 
 pre-\nadder. In this work, we introduce R-Pack, a novel activation- and\nw
 eight-packing technique, able to fully utilize DSP blocks, doubling\ntheir
  multiplication density to boost inference performance. Our\nevaluation sh
 owcases our framework's capabilities in reducing the\ninference latency by
  80% on average, for a mean accuracy loss of\nonly 2.23%, compared to the 
 baseline state-of-the-art hls4ml tool.\n\nTrack: Student\n\n
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