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DTSTAMP:20260730T152640Z
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DTSTART;TZID=America/Los_Angeles:20260728T174000
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UID:dac_DAC 2026_sess306_LBR092@linklings.com
SUMMARY:Late Breaking Results: Scalable OARSMT Generation via Predictive T
 opological Reduction in VLSI Routing
DESCRIPTION:Xiqiong Bai, Daiwei Zhang, and Xiutao Yan (Nanjing University 
 Of Posts And Telecommunications); zhifeng lin (fuzhou university); Kun Wan
 g (Fudan University); Ziran Zhu (School of Integrated Circuits, Southeast 
 University); Jianli Chen (Fudan University); and Zhikuang Cai (Nanjing Uni
 versity Of Posts And Telecommunications)\n\nEfficient OARSMT construction 
 is a critical bottleneck for modern VLSI routing. Current solutions either
  achieve high speed but ignore obstacles, or guarantee legality at the exp
 ense of prohibitive runtimes. In this paper, we introduce a scalable frame
 work that predictively compresses the routing search space without sacrifi
 cing wirelength quality. We first present a learning-guided candidate prun
 ing to condense the obstacle-expanded graph into a set of high-confidence 
 Steiner candidates. Then, we establish a novel Delaunay-driven topological
  sparsification that geometrically confines any optimal obstacle-avoiding 
 rectilinear tree to a linear-size subspace. Evaluations on extreme-density
  benchmarks demonstrate a $1.63\times$ speedup and a 3.2\% wirelength redu
 ction over the state-of-the-art solver. Furthermore, integrating our frame
 work into TritonRoute-WXL reduces the total routing runtime by 7.0\% and w
 irelength by 0.3\% on ICCAD 2019 benchmarks, without introducing any addit
 ional DRC violations.\n\nTrack: Student\n\n
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