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DTSTART:19700308T020000
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DTSTAMP:20260730T152640Z
LOCATION:Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20260728T173600
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UID:dac_DAC 2026_sess306_LBR062@linklings.com
SUMMARY:Late Breaking Results: Unified PCB Routing Considering Pair-Spacin
 g and Width-Range Constraints
DESCRIPTION:Wei-Chen Hung, Jhih-Jie Lee, Sheng-Hua Wang, and Yao-Wen Chang
  (National Taiwan University)\n\nModern printed circuit boards (PCBs), esp
 ecially high-power PCB designs, impose diverse design requirements that de
 mand automated routing. Although grid-based data structures can enforce de
 sign rules, they often incur excessive via usage and long runtimes due to 
 insufficient global planning. This paper presents a constraint-driven rout
 ing framework that systematically addresses these challenges. Our framewor
 k features three key techniques: (1) a crossing-aware global routing metho
 d that models and enforces pair-spacing and width-range constraints, (2) a
  spatial-order preservation strategy that expands the solution space by av
 oiding premature pruning of alternative routing states, and (3) a piecewis
 e net-sizing technique that allocates net widths according to routing reso
 urces while maintaining rule compliance. Experimental results demonstrate 
 the effectiveness of our proposed framework while satisfying all design ru
 les.\n\nTrack: Student\n\n
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