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DTSTAMP:20260730T152640Z
LOCATION:Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20260728T174400
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UID:dac_DAC 2026_sess306_LBR061@linklings.com
SUMMARY:Late Breaking Results: Nano-TSV Assignment for Backside Power Deli
 very Network Designs Considering Stress and IR-Drop Effects
DESCRIPTION:Maoze Liu and Yao-Wen Chang (National Taiwan University) and K
 ai-Yuan Chao (Siemens)\n\nAs resistance and routing congestion intensify a
 t advanced nodes, backside power delivery networks (BSPDNs) have emerged t
 o offload power routing from congested frontside metal. In BSPDNs, nano-th
 rough-silicon vias (n-TSVs) bridge backside power layers to frontside tran
 sistors, and their placement critically impacts IR-drop, thermomechanical 
 stress, and manufacturability. Unlike traditional frontside PDNs, where TS
 V candidates can be placed in general whitespace, BSPDN n-TSVs are constra
 ined to buried power rail (BPR) locations, and their stress effects are no
 n-negligible. Prior staggered assignment schemes mitigate congestion but i
 ntroduce manufacturing complexity and excessive via counts. We present the
  first IR-drop-aware n-TSV optimization flow for BSPDNs under n-TSV densit
 y constraints that enhance packaging manufacturability. We provide a mixed
  integer linear programming (MILP) formulation based on our circuit model 
 for backside power delivery networks. We use efficient model transformatio
 n and legalization methods to obtain our final assignment solutions. Compa
 red with the state-of-the-art staggered assignment method, we reduce the r
 equired number of n-TSVs by an average of 56.68% to satisfy the given IR-d
 rop constraints within a reasonable runtime.\n\nTrack: Student\n\n
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