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DTSTAMP:20260730T152640Z
LOCATION:Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20260728T174700
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UID:dac_DAC 2026_sess306_LBR039@linklings.com
SUMMARY:Late Breaking Results: Merge-Aware Placement and DP-Based Wave Pro
 pagation Routing for Scalable Flip-FET Cell Layout Synthesis
DESCRIPTION:Hao Wu, Fuxing Huang, Qiyuan Chen, Junhong Li, and Keyu Peng (
 Southeast University) and Ziran Zhu (School of Integrated Circuits, Southe
 ast University)\n\nAs transistor scaling advances beyond the 3 nm node, th
 e Flip-FET (FFET) architecture has emerged to provide dual-sided pin acces
 sibility. However, ensuring routable dual-sided connectivity in compact FF
 ET standard cells remains challenging. This work presents a scalable FFET 
 standard cell layout synthesis framework that jointly optimizes transistor
  placement, pin accessibility, and in-cell routing through two tightly cou
 pled optimization phases: a satisfiability modulo theories (SMT)-based mer
 ge-aware transistor placement phase, followed by a dynamic programming (DP
 )-based wave propagation routing phase that integrates dynamic pin assignm
 ent. Experimental results on 3.5T FFET cells show reductions of 5%, 10%, a
 nd 22% in cell width, via count, and wirelength over DAC-25, and 1%, 6%, a
 nd 14% over ASPDAC-26. Furthermore, the proposed framework successfully ro
 utes all 2.5T FFET cells, achieving up to 27% area reduction compared to t
 he corresponding 3.5T designs.\n\nTrack: Student\n\n
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