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BEGIN:VEVENT
DTSTAMP:20260730T152640Z
LOCATION:Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20260728T174200
DTEND;TZID=America/Los_Angeles:20260728T174300
UID:dac_DAC 2026_sess306_LBR007@linklings.com
SUMMARY:Hierarchical ML-Framework for Rapid RDL and Bump Optimisation in G
 PIO-Encroached Flip-Chip SoCs
DESCRIPTION:PRATEEK PENDYALA and Vishant Gotra (Google)\n\nSoC designs fac
 e GPIO encroachment forcing irregular redistribution layer and bump rearra
 ngements on uppermost BEOL metal layers. Optimising density, pitch, and po
 wer grid mesh lacks automated methods. We present a hierarchical two-stage
  ML framework for rapid RDL and bump encroachment modelling in GPIO-constr
 ained flip-chip SoCs. Stage 1 employs classification and regression with s
 liding-window feature aggregation to predict instance-level IR drop. These
  predictions aggregate spatially to tile-level features that feed Stage 2,
  which predicts top-metal voltages for each power net. Validated on indust
 rial sub-micron designs with 25M+ instances, achieving 20-50x acceleration
  with MAE ≤ 1 mV, R2 ≥ 0.995 accuracy. This enables rapid exploration of 1
 00's configurations, saving up to\n25% cost in die area & package penaltie
 s for volume production.\n\nTrack: Student\n\n
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