BEGIN:VCALENDAR VERSION:2.0 PRODID:Linklings LLC BEGIN:VTIMEZONE TZID:America/Los_Angeles X-LIC-LOCATION:America/Los_Angeles BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:19700308T020000 RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:19701101T020000 RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20260730T152730Z LOCATION:Exhibit Hall DTSTART;TZID=America/Los_Angeles:20260728T170000 DTEND;TZID=America/Los_Angeles:20260728T180000 UID:dac_DAC 2026_sess306@linklings.com SUMMARY:Late Breaking Results, Work-in-Progress Poster Session DESCRIPTION:An Autonomous Design Agent of Parallel Feedforward Equalizer f or Advanced Wireline Receivers\n\nFeedforward equalizers (FFEs) are crit ical digital signal processing (DSP) components in ultra-high speed wireli ne receivers, frequently limiting power and area efficiency while requirin g extensive design effort. This work introduces an autonomous design agent that automatically generates FFEs from ...\n\n\nYou-Cheng Tu, Rui-Yong Ku o, and Wei-Zen Chen (NYCU)\n---------------------\nAgentic AI for Chip Des ign and Verification: Results and Limitations from CVDP\n\nWe benchmark a new agentic AI approach for chip design and verification on the CVDP datas et. Our results show that multi-agent orchestration, custom system prompts , and improved tool-use guidance enable our agent to debug and complete su bstantially more complex hardware verification problems. On rel...\n\n\nJa n Ole Ernst and Rajath Salegame (Normal Computing) and Igor Markov (NVIDIA )\n---------------------\nLate Breaking Results: High-Fidelity Simulation and Real-Time Forecasting of Fluid-Solute-Coupled Microfluidics\n\nMicrofl uidic biochips enable complex experiments but lack simulators for coupled physical fields, causing fatal flaws like mixing failure to evade detectio n until post-fabrication. We propose a framework integrating a high-fideli ty fluid-solute-coupled simulator with a graph-transformer forecaster. ... \n\n\nSiyuan Liang (The Chinese University of Hong Kong); Chenghan Wang (C hinese University of Hong Kong); Yushen Zhang (Technical University of Mun ich); Zhiqiang Jia (The Chinese University of Hong Kong); Mengchu Li, Tsu n-Ming Tseng, and Ulf Schlichtmann (Technical University of Munich); and T sung-Yi Ho (The Chinese University of Hong Kong)\n---------------------\nL ate Breaking Results: Micro-Dense Tensor-Core-Aligned N:M Sparse Kernel fo r Efficient Inference Acceleration\n\nSemi-structured N:M sparsity theoret ically reduces arithmetic cost but often fails to deliver proportional end -to-end latency reduction on modern GPUs. We identify that a key bottlenec k lies in irregular execution paths and poor Tensor Core utilization in ex isting sparse kernels. This work presents ...\n\n\nLiu Yiming (University of Science and Technology of China), Wenqi Lou (USTC), Ke Zhiwei (Universi ty of Science&Technology of China), Fengrui Zuo and Chao Wang (University of Science and Technology of China), and Xuehai Zhou (USTC)\n------------- --------\nNPU-Based Energy-Efficient LLM Inference for Semiconductor Equip ment Control Code Generation\n\nIndustrial Algorithmic Pattern Generator ( ALPG) code generation\nwith large language models (LLMs) has shown strong results under\nhigh-cost configurations using proprietary models and GPU-b ased\npipelines. However, such setups limit practical deployment in on-\np remise semiconductor environments. In th...\n\n\nSanghyeok Park, Seunghoo Hong, and Simon Woo (Sungkyunkwan University)\n---------------------\nLate Breaking Results: A Scalable and Efficient Multi-Layer 3D-Printed Microfl uidic Design Synthesis\n\nAdditive manufacturing, or 3D printing, holds gr eat promise for microfluidic fabrication, enabling complex multi-layer 3D layouts, yet practical physical synthesis remains computationally prohibit ive under strict timing and volumetric constraints. In 3D-printed microflu idic devices, precise control ...\n\n\nJiashuo Chen, Yushen Zhang, Tsun-Mi ng Tseng, and Ulf Schlichtmann (Technical University of Munich)\n--------- ------------\nR5-Link : Enhancing RISC-V Multi-Core Efficiency with Hardwa re Message Passing Channels in a 2D Mesh Network\n\nEfficient inter-core c ommunication (ICC) is vital for performance and scalability in multi-core systems. We present R5-Link (RISC-V Link), a hardware–software co-designed ICC mechanism enabling low-latency, contention-free message passing acros s a 2D mesh network. Unlike traditional shared-memory or...\n\n\nYosef Ida , Nachman Abargil, Sarit Shvimer, Alex Grinshpun, and Freddy Gabbay (The H ebrew University)\n---------------------\nSplit–and–Sync Bayesian Learning –Driven SRAM Compiler: Automatic Design Tuning with Optimal Banking\n\nWe propose a Split-and-Sync Bayesian learning framework for SRAM compiler opt imization under macro-level timing and power constraints. The framework de composes these global constraints into leaf-cell-level objectives, where e ach leaf cell—such as a controller, decoder, or peripheral unit—is locally ...\n\n\nJaeseung Baik (Kwangwoon University, Republic of Korea); Ijun Ja ng (Kwangwoon University); Gwanwoo Park (Kwangwoon University, Republic of Korea); Sejun Park and Mingeun Song (Yonsei University, Republic of Korea ); Dahun Ko (Yonsei university); Doohyun Yu (Yonsei University, Republic o f Korea); and Hanwool Jeong (Yonsei University)\n---------------------\nML -Net: Enhanced Interconnect Modeling through Machine Learning–Based Framew ork and Novel Double-π Networks\n\nAccurate timing estimation in VLSI circ uits is strongly influenced by interconnect parasitics. Current timing ana lysis models the distributed RC network as either Lumped-Capacitance or π model. In this work, the Double-π model is introduced as a new RC represen tation that captures higher-o...\n\n\nParsa Mirfasihi and Jatan Mandaliya (San Francisco State University), Omar Yamak and Ahmed Shebaita (Synopsys) , and Hamid Mahmoodi (San Francisco State University)\n------------------- --\nWill AI mess my RTL? A snapshot-based approach to verifying AI-written RTL\n\nWith the growing interest in using AI (Artificial Intelligence) fo r RTL (Register-Transfer Level) hardware development, robust and comprehen sive verification has become more important than ever. As Large Language M odels (LLMs) increasingly assist in creating and modifying RTL designs, en suring that ...\n\n\nBernat Homs and Oscar Palomar (Barcelona Supercomputi ng Center), Miquel Moreto (BSC), and Marcelo Orenes-Vera (NVIDIA)\n------- --------------\nLate-Breaking Results: QML for Quantum Sensing under Measu rement-Induced Information Loss\n\nNitrogen-vacancy (NV) centers in diamon d provide a highly sensi-\ntive platform for quantum sensing. However, ext racting meaningful\ninformation from noisy and lossy measurement data rema ins a ma-\njor challenge. Quantum machine learning (QML) offers a powerful \nframework for parameter estimation by lea...\n\n\nSounak Bhowmik (Southe rn Methodist University) and Himanshu Thapliyal (Southern Methodist Univer sity (SMU))\n---------------------\nLinearly Scalable Algorithms for DFT S tatic Verification, Coverage Analysis, and Debug at RTL\n\nIn this paper, we present DFT static verification and debug as a powerful methodology tha t is scalable to designs with billions of gates. The proposed methodology avoids the pitfalls of alternative approaches such as simulation, formal v erification, and language learning models (LLMs) and complement...\n\n\nKa nad Chakraborty (Real Intent) and Vinod Viswanath (Real Intent, Inc.)\n--- ------------------\nLate Breaking Results: Die Area and Temperature Co-Opt imization for Thermal Throttling Mitigation in Mobile Application Processo rs\n\nTo mitigate workload-driven thermal throttling, advanced mobile pack ages adopt heat escape structures, which can bias the memory interface to one die side and significantly tighten the trade-off between thermally-con strained performance and interconnect length. We formulate thermal throttl ing-aware ...\n\n\nJisoo Hwang (Sungkyunkwan University, Samsung Electroni cs) and SoYoung Kim (Sungkyunkwan University)\n---------------------\nAcce lerated Dynamic Voltage Drop Prediction Using a Lightweight Machine Learni ng Model\n\nAccurate dynamic voltage drop (DVD) analysis is increasingly c ritical in advanced nodes, where higher densities, lower voltages, and com plex packaging exacerbate power delivery challenges. Traditional simulatio ns are computationally expensive and typically performed late in the desig n cycle, risking...\n\n\nItay Yonatanov, Ido Parchomovsky, Mohamad Omari, and Freddy Gabbay (The Hebrew University)\n---------------------\nLate Bre aking Results: Influential Data Selection for LLM-based RTL Generation\n\n Scarcity and noise in open-source datasets severely limit Large Language M odels (LLMs) in Register Transfer Level (RTL) design. To address this, we propose a targeted data selection framework using Low-rank Gradient Simila rity Search (LESS). By leveraging gradient-based influence estimation, LES S fi...\n\n\nZhan Song (University of Maryland, College Park) and Cunxi Yu (University of Maryland/NVIDIA)\n---------------------\nLate Breaking Res ults: Quantum-Aware Model Compression Techniques for Scalable Quantum Mach ine Learning\n\nVariational quantum circuits (VQCs) are promising yet cost ly to deploy because redundant parameters and deep entangling layers ampli fy noise and runtime. We present Q-Compression, a post-training pipeline t hat masks small-magnitude angles, snaps low-sensitivity parameters to a lo w-bit grid using a c...\n\n\nNouhaila Innan (New York University Abu Dhabi ) and Muhammad Shafique (New York University Abu Dhabi (NYUAD))\n--------- ------------\nPASCAL: ML-Based Predictive Skew Compensation for Asymmetric Clock Tree Aging\n\nAsymmetric transistor aging is becoming increasingly significant in advanced process nodes due to rising thermal density and sp atial workload variations. Clock distribution networks are particularly su sceptible, as non-uniform aging across clock branches can distort clock sk ew and lead to setup or h...\n\n\nFreddy Gabbay (The Hebrew University)\n- --------------------\nDefending Side-Channel Attacks in Client-Side Dedupl ication with Hardware/Software Codesign\n\nClient-side deduplication can r educe redundant data transfer, but its duplicate check may expose the file existence status to attackers. Existing software-only defenses provide li mited protection and impose substantial computation. Accordingly, we prese nt RSCD, a Raptor-code and SGX Co-Designed fram...\n\n\nYinjin Fu (Sun Yat -Sen University), Qingli Zeng (University of South Carolina Upstate), and Jian Wu and Nong Xiao (Sun Yat-sen University)\n---------------------\nLat e Breaking Results: Guiding Compiler Optimizations for Neutral Atom Quantu m Computers Through Visualizations\n\nThe scale of Neutral Atom (NA) quant um computers requires automated compilation tools. Designing the required heuristic methods demands a deep understanding of complex hardware trade-o ffs, for which visualizations can provide crucial insights. This work intr oduces NAViz, the first publicly available...\n\n\nYannick Stade and Rober t Wille (Technical University of Munich)\n---------------------\nLate Brea king Results: A Neuromorphic Accelerator for Efficient Multi-Head Attentio n Processing in Spiking Vision Transformers\n\nSpiking Vision Transformers (SViTs) are developed as an energy-efficient alternative to conventional ViTs. To maximize efficiency gains of SViT processing, we propose MorphAtt , a novel digital SViT accelerator that expedites the inference through st reamlined processing. Specifically, it processes mu...\n\n\nRachmad Vidya Wicaksana Putra (New York University (NYU) Abu Dhabi), Amirhesam Jafari Ra d (University of Tehran), and Muhammad Shafique (New York University Abu D habi (NYUAD))\n---------------------\nLate Breaking Results: Q-STEP: A Cro ss-Layer Design and Validation Framework for Advancing Quantum Sensing\n\n Quantum sensing promises measurement sensitivities beyond classical limits , but the study of sensing protocols remains challenging due to limited ac cess to specialized quantum sensing hardware. Existing approaches evaluate sensing protocols using either circuit-level simulations or physics-based sen...\n\n\nGabrielle MacNeil (University of New Hampshire), Hari Paudel (National Energy Technology Laboratory), and Qiaoyan Yu (University of New Hampshire)\n---------------------\nLate Breaking Results: HighTide: an Op en-Source Hardware Benchmark Suite\n\nEvaluation of Electronic Design Auto mation (EDA) tools, circuits, and systems often relies on outdated hardwar e benchmarks. Existing benchmark designs, which are predominantly RISC-V C PUs, provide limited representation of components found in modern SoCs. Th is hinders (i) evaluating the capabilities...\n\n\nBenjamin Goldblatt, Pao lo Pedroso, Farhad Modaresi, and Matthew Guthaus (University of California , Santa Cruz)\n---------------------\nA novel way to handle non-convergenc e of properties in formal verification of digital systems\n\nThe increasin g complexity of modern digital designs presents significant challenges for formal verification, particularly when properties fail to converge within practical proof bounds. Non-convergent assertions hinder verification sig n-off and limit the ability to expose deep corner-case bugs. This...\n\n\n surinder sood, kishan mushar, and Nirmal Jose (ARM)\n--------------------- \nLate Breaking Results: Energy-Aware Scheduling of Open-Vocabulary Detect ion on Low-Power Mobile Robots\n\nOpen-vocabulary object detection enables language-driven object search for mobile robots, but on embedded GPUs a f ixed 8 Hz detector can dominate the mission energy budget. We propose an\n energy-aware runtime that couples a tri-state scheduler (SLEEP/EXPLORE/TRA CK at 1.5/4/8 Hz) with dual-precision s...\n\n\nAbdul Basit, Nurik Serikba yev, and Muhammad Shafique (New York University Abu Dhabi (NYUAD))\n------ ---------------\nLate Breaking Results: A Resource-Constrained Co-Design F ramework for Enabling Heterogeneous Quantum Chiplet Ensembles via Circuit Cutting\n\nNear-term (NISQ) quantum processors are limited in qubit count, connectivity, and coherence, which constrains the size of quantum neural networks (QNNs) that can run monolithically on a single device. We propose a heterogeneous chiplet \emph{ensemble} architecture that targets a reali stic setting wi...\n\n\nAlberto Marchisio (New York University Abu Dhabi ( NYUAD)); Muhammad Kashif (eBrain Lab, Division of Engineering, New York Un iversity (NYU) Abu Dhabi, UAE); Nouhaila Innan and Walid El Maouaki (New Y ork University Abu Dhabi); and Muhammad Shafique (New York University Abu Dhabi (NYUAD))\n---------------------\nLate Breaking Results: Analog Circu it Sizing via LLM-Guided Heuristic Search with Metric Difficulty Awareness \n\nAnalog sizing remains challenging since circuit parameters vary signif icantly across different Process Design Kits (PDKs) and circuit topologies . While recent AI-based approaches attempt to automate this process, many rely on large models or struggle to generalize across technology nodes. Th is paper...\n\n\nXinyue Wu, Fan Hu, Jani Shaik, and Zixuan Li (Shanghai Ji ao Tong University); Mohamed El-Hadedy (CalPoly Pomona); and Xinfei Guo (S hanghai Jiao Tong University)\n---------------------\nLate Breaking Result s: Encoding-in-Memory via Generating True Random One-time Password\n\nTrue Random Number Generators (TRNGs) are essential for hardware security, yet existing DRAM-based designs primarily extract entropy into external buffe rs for cryptographic use, increasing exposure to leakage and profiling att acks. This work introduces Encoding-In-Memory TRNG (EIM-TRNG), a DRAM-base ...\n\n\nRanyang Zhou and Gamana Aragonda (New Jersey Institute of Technol ogy), Abeer Almalky (Binghamton University (SUNY)), Filip Roth Tronnes-Chr istensen (New Jersey Institute of Technology), Adnan Siraj Rakin (Binghamt on University), and Shaahin Angizi (New Jersey Institute of Technology)\n- --------------------\nHierarchical Learning–Based Digital Circuit Design T uning Framework for Power-Delay Optimization\n\nWe present a learning-base d transistor-level design optimization framework for digital logic circuit s that fully regenerates schematics and layouts after synthesis or place-a nd-route. Unlike conventional gate-level optimization limited to fixed sta ndard-cell variants, it directly tunes transistor pa...\n\n\nIjun Jang (Kw angwoon University); Jaeseung Baik and Gwanwoo Park (Kwangwoon University, Republic of Korea); Sejun Park and Mingeun Song (Yonsei University, Repub lic of Korea); Dahun Ko (Yonsei university); Doohyun Yu (Yonsei University , Republic of Korea); and Hanwool Jeong (Yonsei University)\n------------- --------\nLate Breaking Results: Analog Circuit Sizing Optimization using Procrustes-Guided Machine Learning Heuristics\n\nAutomated chip design tec hniques are commonplace in digital IC design. Hardware description languag es and register-transfer logic (RTL) code allow a design to be abstracted beyond a specific process. However, analog circuit performance is inherent ly tied to the specific technology and tradeoffs made...\n\n\nBrandon Hipp e and David Burnett (Villanova University) and Lydia Lee (Sandia National Laboratories)\n---------------------\nLate Breaking Results: Fast Energy-A ware Neural Network Modeling for Efficient FPGA-Based Inference\n\nFPGAs p rovide customizable hardware acceleration that enables efficient, low-late ncy execution of machine learning inference through application-specific p arallelism. While resource utilization and latency can typically be estima ted early in the design process, accurate power consumption analysis ge... \n\n\nRishi Agrawal (BITS Pilani, Hyderabad Campus) and Andrea Guerrieri ( EPFL and HES-SO)\n---------------------\nLate Breaking Results: FeMFET Mul ti-Level Cell Capacity Limits for SNN-Based Compute-in-Memory Inference\n\ nFeMFET multi-level cell (MLC) operation promises high-density weight stor age for spiking neural network (SNN) inference in compute-in-memory (CIM) systems. We characterise 60 FeMFET devices and show that 4-state operation produces an S2-S3 threshold-voltage separation of only 1.12 sigma (21.5% read ...\n\n\nOsama Abdelaal (Fraunhofer IPMS CNT), Alptekin Vardar (Fraun hofer IPMS), Nandakishor Yadav (Indian Institute of Technology Indore), an d Thomas Kämpfe (Fraunhofer IPMS)\n---------------------\nLate Breaking Re sults: Hardware-Efficient PQ Search Framework for Sparse Coding-Based KV C ache Compression\n\nThis paper proposes an OPQ-based two-stage search fram ework for efficient sparse coding in KV cache compression. By integrating Optimized Product Quantization (OPQ) with a filter-and-refine strategy, ou r framework identifies a compact candidate subset using compressed metadat a before performing exac...\n\n\nSohyeon Kim (Hanyang University); Doohyun Cho (D.Notitia Inc.,); Myounghoon Cho, Donghoon Han, and SeungJae Lee (Dn otitia Inc.); and Ji-Hoon Kim (Hanyang University)\n---------------------\ nLate Breaking Results: Synthesizable 8-Bit Digital Memristor Emulator wit h Programmable State Retention for Accelerated Edge Computing\n\nMemristiv e devices are promising for neuromorphic and in-memory computing, but prac tical analog implementations often face variability and fabrication challe nges. This work presents a synthesizable 8-bit digital memristor emulator implemented in Verilog and targeted for FPGA realization. The design ...\n \n\nShekhar Suman Borah and Philip Waldecker (Center for Robotics and Inte lligent Systems, The University of Texas at Tyler, Tyler, Texas, USA); Hen ry Torbert (National Soil Dynamics Lab, USDA-ARS); and Prabha Sundaravadiv el (Associate Professor, The University of Texas at Tyler)\n-------------- -------\nLockRoute: A Spatial Locking Framework for Parallel Global Routin g\n\nGlobal routing is a crucial step in VLSI design that has become incre asingly more complex as chip sizes and design scales grow. Many global rou ters divide the process into several stages: two-pin decomposition, conges tion map generation, maze routing and layer assignment. Each of these stag es requir...\n\n\nAmber Thrall (Washington State University), Vidya Chhabr ia (Arizona State University), S. M. Ferdous and Mahantesh Halappanavar (P acific Northwest National Laboratory), and Bala Krishnamoorthy (Washington State University)\n---------------------\nLate Breaking Results: Tiny Bra in, Big World: Autonomous MCU-Friendly Navigation for Mapless Dynamic Envi ronments\n\nWe present a lightweight, mapless path-planning framework for resource-constrained robots operating in dynamic environments. The method incrementally builds small local maps from onboard sensors, selects interm ediate subgoals, and applies A* planning only within these local regions t o navigate step-...\n\n\nOmer Kurkutlu and Arman Roohi (University of Illi nois Chicago)\n---------------------\nLate Breaking Results: Unified PCB R outing Considering Pair-Spacing and Width-Range Constraints\n\nModern prin ted circuit boards (PCBs), especially high-power PCB designs, impose diver se design requirements that demand automated routing. Although grid-based data structures can enforce design rules, they often incur excessive via u sage and long runtimes due to insufficient global planning. This pa...\n\n \nWei-Chen Hung, Jhih-Jie Lee, Sheng-Hua Wang, and Yao-Wen Chang (National Taiwan University)\n---------------------\nLate Breaking Results: A Fully Differentiable Rectilinear Minimum Spanning Tree Wirelength Model for Glo bal Placement\n\nGlobal placement relies heavily on differentiable wirelen gth models to guide the optimization process. While the half-perimeter wir elength is gold standard due to its computational efficiency and smooth ap proximations, it suffers from a significant fidelity gap as it fails to ca pture the internal ro...\n\n\nFuxing Huang, Hao Wu, Junhong Li, and Qiyuan Chen (Southeast University); Wenxing Zhu (Fuzhou University); xinning liu (southeast university); and Ziran Zhu (School of Integrated Circuits, Sou theast University)\n---------------------\nLate Breaking Results: Efficien t MoE-ViT Gating on Edge Accelerator via Dynamic Expert Routing and Quanti zed Router\n\nWe propose a dynamic routing strategy that adapts expert usa ge to input difficulty while reducing overall computation. We also quantiz e the gating weights using a multiplier-free scheme and apply\npost-traini ng calibration to preserve routing decisions. Compared with Top-K routing, dynamic routing im...\n\n\nZheqi He, Zhendong Zheng, and teng wang (Unive rsity of Science and Technology of China); Nanhao Zhou (13915576921); Lei Gong (University of Science and Technology of China); Wenqi Lou (USTC); Ch ao Wang (University of Science and Technology of China); and Xuehai Zhou ( USTC)\n---------------------\nLate Breaking Results: Physics-Aware Diffusi on Framework for Transistor-Level Placement Beyond Standard-Cell Boundary\ n\nAs conventional standard-cell methodologies increasingly limit Design T echnology Co-Optimization (DTCO) in advanced nodes, direct transistor-leve l placement emerges as a crucial solution for minimizing wirelength and ar ea. However, existing analytical placers optimize continuous coordinates, struggl...\n\n\nKeyu Peng, Junhong Li, Hao Wu, Chao Wang, and Jun Yang (So utheast University) and Ziran Zhu (School of Integrated Circuits, Southeas t University)\n---------------------\nLate Breaking Results: LLM-Driven Co nstraint Generation and Deferred Shape Exploration for Analog IC Floorplan ning\n\nAnalog integrated circuit (IC) layout automation is fundamentally hindered by the semantic gap in constraint extraction and the premature bi nding of device shapes. Traditional serial flows rely on simplistic, netli st driven constraint handling and decouple device generation from floorpla nning. This ...\n\n\nYu Chen and Fuxing Huang (Southeast University); Chen gjie Liu (Nanjing University); Xi Wang (Southeast University); and Ziran Z hu (School of Integrated Circuits, Southeast University)\n---------------- -----\nLate Breaking Results: Power Mesh Construction for 3D-IC with Backs ide Power Delivery\n\nA 3D-IC architecture packs a design with enhanced fu nctionality\nand density into a small footprint while improving performanc e\nand lowering costs. By leveraging through-silicon via (TSV) and\ndie-to -die bump technology, power can be efficiently delivered to\nthe top and b ottom dies. Moreover, advanced...\n\n\nChien-Pang Lu (Intel), Chun-Hao Lai and Iris Hui-Ru Jiang (National Taiwan University), and Chih-Hsiang Yang and Chung-Ching Peng (Intel)\n---------------------\nDScNMP: A Dataflow Sc heduling for the Precision-Scalable Near-memory Processing Microarchitect ure\n\nNear-memory processing (NMP) mitigates the overhead of host-memory data movement while maintaining efficient data access.\nWe introduce DScNM P, an architecture-dataflow co-design that employs dataflow scheduling to optimize NMP executions.\nDScNMP incorporates dynamic workload scheduling, intra-cycle ...\n\n\nyueting Li (Hangzhou International Innovation Instit ute, Beihang University)\n---------------------\nLate Breaking Results: AS TFusion -- Two-Stage Structural Enhancement Learning for Robust HLS Code Generation\n\nRecent studies show that abstract syntax trees (ASTs) can im prove the syntactic validity of large language model (LLM)-generated high- level synthesis (HLS) code. However, structure-enhanced methods often degr ade at inference due to reliance on explicit structural signals during tra ining. We show tha...\n\n\nKe Zhiwei (University of Science&Technology of China); Wenqi Lou (USTC); Liu Yiming, Fengrui Zuo, and Chao Wang (Universi ty of Science and Technology of China); and Xuehai Zhou (USTC)\n---------- -----------\nLate Breaking Results: Toward a Foundation Model for 3DIC The rmal Analysis and Beyond\n\nThermal management in 3DIC designs is critical due to high power density from vertically stacked dies. While FEM-based t hermal analysis provides accurate results, it is computationally prohibiti ve for design space exploration. We present a generic 3DIC multi-physics f oundation model architecture tha...\n\n\nAkhilesh Kumar (Synopsys); Zelin Lu (University of Maryland, College Park); Norman Chang (Synopsys); Igor M arkov (NVIDIA); Lang Lin, Jessica Yen, Haoliang Jiang, Wenbo Xia, and Yuji ng Luo (Synopsys); and Gang Qu (Univ. of Maryland, College Park)\n-------- -------------\nAutomated Design of Device Fingerprinting Circuits for FPGA s\n\nDesigning device fingerprinting circuits for FPGAs is challenging due to limited knowledge about device layout and manufacturinginduced biases, often resulting in poor uniqueness and biased responses. Existing mitigat ion techniques are typically device-specific, time-consuming, and difficul t to gene...\n\n\nJames Moore, Maire O'Neill, and CHONGYAN GU (Queen's Uni versity Belfast)\n---------------------\nLate Breaking Results: Recoverabi lity-guided Layer-wise N:M Sparsity under Latency Constraints\n\nLayer-wis e N:M sparsity balances accuracy and hardware acceleration for Vision Tran sformers (ViTs), yet identifying effective configurations is costly due to fine-tuning overhead and latency-induced fragmentation. We present HaLSpa r, a hardware-aware framework that couples a recoverability-driven ze...\n \n\nLiu Yiming (University of Science and Technology of China), Wenqi Lou (USTC), Ke Zhiwei (University of Science&Technology of China), Fengrui Zuo and Chao Wang (University of Science and Technology of China), and Xuehai Zhou (USTC)\n---------------------\nNeural Subgraph Matching for Hardware Decompilation in Gate-Level Netlists\n\nModern IC globalization and autom ated synthesis often produce flattened netlists that obscure design intent , complicating hardware security analysis and reverse engineering. Traditi onal decompilation methods based on exact subgraph isomorphism or fixed li braries are computationally expensive and str...\n\n\nYunzhen Liu (Univers ity of Massachusetts Amherst), Yingjie Li (Simon Fraser University), and N an Wu (George Washington University)\n---------------------\nLate Breaking Results: 3D Analytical Placement with Smoothed Multi-die Wirelength Model \n\nHeterogeneous integration via hybrid bonding optimizes power, performa nce, and area (PPA) in multi-die systems. A core challenge is assigning ci rcuit blocks to dies in different process technologies. Existing analytica l formulations employ smoothly varying sigmoid proxies, causing assignment oscilla...\n\n\nXingyu Tong (Fudan University), Chih-Jung Hsu (National T aiwan University), Guohao Chen (Fudan University), Yin-Hsuan Hung (Nationa l Taiwan University), Jianli Chen (Fudan University), and Yao-Wen Chang (N ational Taiwan University)\n---------------------\nLate Breaking Results: "Describing" Your Way to a Functional Microfluidic Chip\n\nMicrofluidic de vices enable miniaturized, automated laboratory operations, but their desi gn typically requires specialized expertise and labor-intensive CAD workfl ows. We present a language-driven framework that synthesizes manufacturabl e microfluidic designs directly from natural-language prompts. ...\n\n\nYu shen Zhang and Louis Dickgießer (Technical University of Munich), Siyuan L iang (The Chinese University of Hong Kong), Tsun-Ming Tseng (Technical Uni versity of Munich), Shigeru Yamashita (Ritsumeikan University), Tsung-Yi H o (The Chinese University of Hong Kong), and Ulf Schlichtmann (Technical U niversity of Munich)\n---------------------\nLate Breaking Results: Scalab le OARSMT Generation via Predictive Topological Reduction in VLSI Routing\ n\nEfficient OARSMT construction is a critical bottleneck for modern VLSI routing. Current solutions either achieve high speed but ignore obstacles, or guarantee legality at the expense of prohibitive runtimes. In this pap er, we introduce a scalable framework that predictively compresses the rou ting se...\n\n\nXiqiong Bai, Daiwei Zhang, and Xiutao Yan (Nanjing Univers ity Of Posts And Telecommunications); zhifeng lin (fuzhou university); Kun Wang (Fudan University); Ziran Zhu (School of Integrated Circuits, Southe ast University); Jianli Chen (Fudan University); and Zhikuang Cai (Nanjing University Of Posts And Telecommunications)\n---------------------\nLate Breaking Results: QUBO Approaches to Logic Equivalence Checking and Testin g\n\nThis work presents a novel approach to formulate Logic Equivalence Ch ecking (LEC) and Test Pattern Generation (TPG) problems as Quadratic Uncon strained Binary Optimization (QUBO) formulations, allowing them to be solv ed with quantum algorithms such as Quantum Annealing and Quantum Approxima te Optimi...\n\n\nTao-Chun Huang, Hao-Yu Tsai, You-Cheng Lin, Yi-Ting Li, and Wuqian Tang (National Tsing Hua University); Yung-Chih Chen (National Taiwan University of Science and Technology; Arculus System Co. Ltd.); Jia n-Meng Yang (ARCULUS SYSTEM CO., LTD.); and Chun-Yao Wang (Dept. CS, Natio nal Tsing Hua University)\n---------------------\nPolaris: Enabling PIM-Op timized Low-Energy SpGEMM using a Remote-Access-Aware Mapping Solution\n\n Sparse kernels are widely used in applications ranging from scientific com puting to machine learning. Among them, SpGEMM is particularly challenging due to irregular memory accesses, making it highly memory-bound and domin ated by data movement. Processing-in-Memory architectures can mitigate thi s co...\n\n\nHelya Hosseini (University of Maryland, College Park); Christ ina Giannoula (Max Planck Institute for Software Systems); and Bahar Asgar i (University of Maryland, College Park)\n---------------------\nLate Brea king Results: Novel Qubit Mapping for Two-Dimensional Trapped-Ion Quantum Computing Systems\n\nEffective qubit mapping facilitates quantum algorithm implementations in physical quantum computing architectures. Recent work reported promising qubit mapping on one-dimensional trapped-ion systems. D ue to manufacturing complexity, however, it is insufficient to map all log ical qubits into one sing...\n\n\nWei-Hsiang Tseng (The Electronic Design Automation Laboratory Graduate Institute of Electronics Engineering Nation al Taiwan University) and Yao-Wen Chang and Jie-Hong Roland Jiang (Nationa l Taiwan University)\n---------------------\nLate Breaking Results: HUSH: Silencing Inter-Core Interference in Real-Time Cache Analysis\n\nStatic wo rst-case execution time (WCET) analysis for multicore real-time systems re mains pessimistic because write-invalidate coherence perturbs remote cache states at run time, preventing per-core hit/miss classification. We prese nt HUSH, a write-update coherence that silences interference while bo...\n \n\nHaoyuan Ren (University of science and technology of China); Yinkang G ao (Department of Computer Science and Technology, University of Science a nd Technology of China); Yixuan Zhu, Bo Zhang, and teng wang (University o f Science and Technology of China); Wenqi Lou (USTC); and Xi Li (Universit y of Science and Technology of China)\n---------------------\nLate Breakin g Results: Hardware-Aware Compilation Reshapes Trainability in Variational Quantum Circuits\n\nVariational quantum circuits (VQCs) are typically eva luated at the logical design level when analyzing trainability. However, e xecution on real quantum devices requires hardware-aware compilation to sa tisfy qubit connectivity and gate constraints. \nIn this paper, we examine how transpilation alone a...\n\n\nMuhammad Kashif (eBrain Lab, Division o f Engineering, New York University (NYU) Abu Dhabi, UAE) and Muhammad Shaf ique (New York University Abu Dhabi (NYUAD))\n---------------------\nHiera rchical ML-Framework for Rapid RDL and Bump Optimisation in GPIO-Encroache d Flip-Chip SoCs\n\nSoC designs face GPIO encroachment forcing irregular r edistribution layer and bump rearrangements on uppermost BEOL metal layers . Optimising density, pitch, and power grid mesh lacks automated methods. We present a hierarchical two-stage ML framework for rapid RDL and bump en croachment modelling in ...\n\n\nPRATEEK PENDYALA and Vishant Gotra (Googl e)\n---------------------\nLate Breaking Results: Structured Expert Routin g for Efficient MoE Inference under GPU–CPU Orchestration\n\nHybrid GPU–CP U deployment of large Mixture-of-Experts (MoE) models is often latency-bou nd by CPU–side expert execution and cross-device orchestration overhead. T o overcome this limitation, we propose a structured expert routing strateg y, implemented via asymmetric expert skipping, which reduces expe...\n\n\n Yixiao Chen, Arman Akbari, and Arash Akbari (Northeastern University); Zhe ndong Mi (Stevens Institute of Technology); Enfu Nan (Northeastern Univers ity); Xiaowei Lin (ETH Zurich); Weiwei Chen (EmbodyX Inc.); Shaoyi Huang a nd Hao Wang (Stevens Institute of Technology); and Pu Zhao and Yanzhi Wang (Northeastern University)\n---------------------\nLate Breaking Results: EIV-Aware Backside PDN Synthesis Under Strict nTSV Spacing Constraints\n\n Backside power delivery networks (BSPDNs) alleviate front-side routing con gestion, yet they introduce new challenges, including high resistance of b uried power rails (BPRs) and nano-through-silicon vias (TSVs), as well as stringent TSV spacing constraints. This paper presents the first power-awa re B...\n\n\nYin-Qi Xu and Shao-Yun Fang (National Taiwan University of Sc ience and Technology)\n---------------------\nLate Breaking Results: A Hig h-Performance TFHE Bootstrapping Accelerator with Heterogeneous Processing Engines\n\nThis paper presents a high-performance programmable bootstrapp ing (PBS) accelerator for privacy-preserving computation under Torus Fully Homomorphic Encryption (TFHE) scheme. The proposed design features a hete rogeneous processing architecture, including a barrel-shifter-based polyno mial rotation un...\n\n\nHaopeng Zhang and Yukui Luo (Binghamton Universit y), Jiafeng Xie (Villanova University), and Wenfeng Zhao (Binghamton Unive rsity)\n---------------------\nLate Breaking Results: A Coarse-to-Fine PCB Placement Framework via LLM-Guided Component Grouping and Group-Aware Pla cement\n\nThis paper introduces a coarse-to-fine printed circuit board (PC B) placement framework bridging high-level functional design intent and ph ysical implementation. First, a large language model (LLM)-guided componen t grouping engine utilizes multi-modal feature serialization, topology-enr iched retrieva...\n\n\nJunhong Li, Keyu Peng, Fuxing Huang, and Hao Wu (So utheast University) and Ziran Zhu (School of Integrated Circuits, Southeas t University)\n---------------------\nSAT-Helper: A Multi-Agent System for Adaptive Optimizing Large-Scale Conjunctive Normal Form\n\nLarge-scale CN Fs exceed LLM context windows, and direct rewriting can break equivalence. SAT-Helper is a zero-shot multi-agent CNF optimizer that samples sliding windows, selects small high-impact blocks and local strategies, rewrites o nly those blocks, and accepts updates only after SAT-based equiv...\n\n\nZ hiyuan HE and Rongliang Fu (The Chinese University of Hong Kong), Pin-Yu C hen (IBM Research), and Tsung-Yi Ho (The Chinese University of Hong Kong)\ n---------------------\nLate Breaking Results: A Unified Analytical Framew ork for MBFF Clustering and Placement for Timing, Power, and Area Co-Optim ization\n\nThis paper presents a unified analytical multi-bit flip-flop (M BFF) clustering and placement framework that addresses industrial compatib ility constraints while jointly optimizing timing, power, and area. Our fr amework combines (1) efficient timing and power models, (2) prioritized mu lti-density map...\n\n\nChuan-Chi Su, Yu-Sheng Yang, Cheng-Yen Li, Shao-Hs iang Chen, and Yao-Wen Chang (National Taiwan University)\n--------------- ------\nLate Breaking Results: Nano-TSV Assignment for Backside Power Deli very Network Designs Considering Stress and IR-Drop Effects\n\nAs resistan ce and routing congestion intensify at advanced nodes, backside power deli very networks (BSPDNs) have emerged to offload power routing from congeste d frontside metal. In BSPDNs, nano-through-silicon vias (n-TSVs) bridge ba ckside power layers to frontside transistors, and their placement c...\n\n \nMaoze Liu and Yao-Wen Chang (National Taiwan University) and Kai-Yuan Ch ao (Siemens)\n---------------------\nLate Breaking Results: ROAST: Reverse -training Offset Attack on Spatial Sampling Topologies\n\nLocal Binary Pat tern Network (LBPNet) concentrates representational power in a small set o f learned spatial sampling offsets, creating a high-leverage fault surface . We propose ROAST, a white-box reverse-training attack that updates only offsets to maximize the loss, then maps adversarial offsets to...\n\n\nSha yan Gerami (Student), Sepehr Tabrizchi (University of Illinois Chicago), S haahin Angizi (New Jersey Institute of Technology), and Arman Roohi (Unive rsity of Illinois Chicago)\n---------------------\nLate Breaking Results: Training-Free CCS Library Generation via Voltage Domain Transformation and PCHIP Interpolation\n\nAccurate timing-library generation across PVT cond itions has become increasingly expensive in advanced technology nodes. Thi s paper introduces a robust, training-free method for inferring CCS librar y entries at target PVT corners by interpolating voltage waveforms, rather than currents, using shape-...\n\n\nMeng-Hsuan Ho (National Yang Ming Chi ao Tung University); Hung-Ming Chen (Institute of Electronics, National Ya ng Ming Chiao Tung University); and Hsuan-Ming Huang and Jiun-Cheng Tsai ( Mediatek)\n---------------------\nLate-Breaking Results: Ultra Energy Effi cient Personalized Glucose Prediction with RLS Implementation on a Tiny FP GA\n\nAccurate prediction of future blood glucose (BG) levels is critical for\nthe effective management of type 1 diabetes. Existing approaches\nfor glucose prediction often rely on deep learning models that are\ncomputati onally intensive. In this work, we propose an adaptive and\nlightweight re cursive least ...\n\n\nGeorgios Mentzos (Karlsruhe Institute of Technology ), Theodora Podimata (University Of Patras), Georgios Zervakis (National T echnical University of Athens), Emmanouil Psarakis (University of Patras), and Joerg Henkel (KIT)\n---------------------\nLate Breaking Results: Hyb rid-Bonding Architecture with Stage-Aware Mapping for Masked Autoregressiv e Model Inference\n\nMasked autoregressive (MAR) models have recently show n strong potential in visual generation tasks. Unlike traditional autoregr essive model that generates tokens sequentially, MAR predicts multiple tok ens in parallel at each generation step (stage), resulting in non-linear g rowth in computation and ...\n\n\nWenxi Gao (Imperial College London), Zhe nhua Zhu (Tsinghua University), Hongyi Wang (HKUST), Yuan Xie (Hong Kong U niversity of Science and Technology), and Yu Wang (Tsinghua University)\n- --------------------\nLate Breaking Results: Hardware-Efficient Quantum Re servoir Computing via Quantized Readout\n\nDue to rising electricity deman d, accurate short-term load forecasting is increasingly important for grid stability and efficient energy management, particularly in resource-const rained edge settings. We present a hardware-efficient Quantum Reservoir Co mputing (QRC) framework based on a fixed, untra...\n\n\nParam Pathak (Quan tumAI Lab, Fractal Analytics); Mansi Od (University of Greenwich); Nouhail a Innan (New York University Abu Dhabi); and Muhammad Shafique (New York U niversity Abu Dhabi (NYUAD))\n---------------------\nLate Breaking Results : Audio-Language-Action Models with Direct Speech Conditioning for Robotic Manipulation\n\nVision-language-action (VLA) models enable robots to foll ow instructions in typed text, limiting broader deployment in natural spee ch.The traditional solution by prepending a speech recognition before VLA to convert speech into texts would incur additional latency and propagate errors. To address th...\n\n\nEnfu Nan, Pu Zhao, Yixiao Chen, and Lin Zhao (Northeastern University); Juyi Lin (NEU); Chen Wang and Weiwei Chen (Emb odyX Inc.); and Yanzhi Wang (Northeastern University)\n------------------- --\nLate Breaking Results: Merge-Aware Placement and DP-Based Wave Propaga tion Routing for Scalable Flip-FET Cell Layout Synthesis\n\nAs transistor scaling advances beyond the 3 nm node, the Flip-FET (FFET) architecture ha s emerged to provide dual-sided pin accessibility. However, ensuring routa ble dual-sided connectivity in compact FFET standard cells remains challen ging. This work presents a scalable FFET standard cell layout sy...\n\n\nH ao Wu, Fuxing Huang, Qiyuan Chen, Junhong Li, and Keyu Peng (Southeast Uni versity) and Ziran Zhu (School of Integrated Circuits, Southeast Universit y)\n---------------------\nLate Breaking Results: Fisher-Guided Selective Error Reconstruction for Quantized LLMs\n\nWe propose FOCUS, a hardware-aw are PTQ recovery framework for low-bit LLM inference. FOCUS uses Fisher in formation to select approximately 1.5% structurally critical row-column in tersections and optimizes their corrections via ridge regression to match output error, enabling a small set of parameter...\n\n\nSeonha Ryu (DGIST) , Il Hong Suh (coga-robotics), and Yeseong Kim (DGIST)\n------------------ ---\nLate Breaking Results: Towards Low-Latency TinyML via Regularized Act ivation Packing\n\nIn recent years, customized and low-precision CNNs have emerged,\ntailored for TinyML applications and well-suited for FPGA deplo y-\nment. DSP Packing has been proposed to increase the computa-\ntional d ensity of the limited DSP blocks on modern FPGAs, but\ncurrent solutions u nder-utilize key DSP compon...\n\n\nGeorgios Mentzos (Karlsruhe Institute of Technology), Konstantinos Balaskas (University of Patras), Georgios Zer vakis (National Technical University of Athens), and Joerg Henkel (KIT)\n- --------------------\nAccelerating Functional Fault Grading for Flash and DRAM Designs\n\nFunctional fault grading is essential for post-silicon val idation in scan-limited designs, but simulation cost grows with fault and pattern volume. We propose an optimization-driven methodology combining st atic fault optimization, fault clustering, design pruning, stimulus gradin g, dynamic fault opt...\n\n\nEuisang Yoon, Arun Gogineni, and Saurabh Sriv astava (Siemens); Eunjong Oh and Seongwook Lee (Samsung Electronics); Sung yun Yoo and Geonbeom Kwon (Siemens); and Yoseop Lee and Hyojin Choi (Samsu ng Electronics)\n---------------------\nChipLite: High-level Performance M odeling Methodology for Automotive Chiplet Systems\n\nAs automotive comput e platforms evolve toward chiplet-based\narchitectures, the increasing het erogeneity introduces new challenges\nin exploring the architecture design space as a function of\nmetrics such as performance, power, area, and cos t. In this pursuit,\ntraditional high-fidelity methodologies, ...\n\n\nDik sha Moolchandani and Vinay Kumar (IMEC)\n---------------------\nEdgeQ‑GEMM : INT4/INT8 Mixed‑Precision GEMM Accelerator with On‑the‑Fly Quantization for Accuracy–Energy Tunability in Edge AI Processors\n\nEdge workloads suc h as keyword spotting and activity recognition must process continuous FP3 2 sensor data under tight power–performance–area budgets, making full-prec ision GEMM units impractical. EdgeQ-GEMM is a compact, processor-integrate d INT4/INT8 mixed-precision GEMM accelerator tha...\n\n\nChaebin Jung, Kye ongwon Lee, Hyunseok Kwak, Jongin Choi, Sechan Park, and Sangmin Jeon (Chu ng-Ang University); Hyeonguk Jang and Jae-Jin Lee (ETRI); and Woojoo Lee ( Chung-Ang University)\n---------------------\nSwift-Healer: Firmware-Recon figurable Self-Healing for Remote Glitch-Injection on Autonomous Driving S ystems\n\nAutonomous Navigation Systems (ANS) incorporate many safety-crit ical functions, such as collision avoidance. Recent studies have shown how remote clock/voltage glitch injections pose an imminent threat to mission -sensitive modules in the autonomous navigation domain: timing/power pertu rbations in th...\n\n\nAli Suvizi and Joshua Iwu (Electrical and Computer Engineering, The George Washington University); Kostas Amberiadis (Nationa l Institute of Standards and Technology (NIST)); and Guru Venkataramani (E lectrical and Computer Engineering, The George Washington University)\n--- ------------------\nThe Last Line of Defense in DNN inference: ArgMax Secu rity under Combined Power Side-Channel and Fault Injection Attack\n\nDeep Neural Network (DNN) edge devices are increasingly vulnerable to severe ha rdware security threats, particularly side-channel attacks (SCA) and fault injection attacks (FIA). This paper, for the first time, presents a combi ned side-channel and fault injection attack framework targeting the ArgMa. ..\n\n\nLe Wu and Liji Wu (School of Integrated Circuits, Beijing National Research Center for Information Science and Technology, Tsinghua Universi ty, Beijing, China); Yuyang Pan (Beijing Unionpay Card Technology Co.,Ltd) ; and Xiangmin Zhang (School of Integrated Circuits, Beijing National Rese arch Center for Information Science and Technology, Tsinghua University, B eijing, China)\n---------------------\nCompact ML-based glitch propagation modeling of standard cells\n\nWith continuous technology scaling, accurat e and efficient glitch modeling is critical for designing energy-efficient and reliable ICs. In this work, we present a new gate-level approach for glitch propagation modeling, utilizing Artificial Neural Networks (ANNs) t o estimate the key glitch shape cha...\n\n\nAnastasis Vagenas, Dimitrios G aryfallou, and George Stamoulis (University of Thessaly)\n---------------- -----\nRELMAS-HRT: Online Inference Scheduling in Mixed-Criticality Multi- Tenant Multi-Accelerator Systems via Reinforcement Learning\n\nWe present RELMAS-HRT, an online reinforcement learning scheduler for heterogeneous m ulti-accelerator systems (MAS) that guarantees hard real-time (HRT) deadli nes while optimizing QoS for multi-tenant DNN inference. The framework adm its HRT tasks through a WCET-based feasibility test, constructs a d...\n\n \nFrancesco Blanco and Enrico Russo (Univerisity of Catania) and Giuseppe Ascia and Maurizio Palesi (University of Catania)\n---------------------\n Nucleus: A Reconfigurable Long-Context LLM Accelerator Using Adaptive Outl ier-Aware KV Cache Quantization\n\nLarge Language Models (LLMs) face signi ficant compute and memory bottlenecks from massive key-value data in long- context inference. We present Nucleus, a configurable accelerator that app lies online outlier-aware quantization to reduce TTFT and TBT. Its runtime -configurable outlier detector dynamica...\n\n\nYoungmin Cho (Ajou Univers ity), Yoontae Lee (University College London), Lojin Park (KAIST (Korea Ad vanced Institute of Science and Technology)), Sunjae Lee (Sungkyunkwan Uni versity), Jimin Lee (Carnegie Mellon University), Jeongwoo Park (Sungkyunk wan University), and Young Oh (Ajou University)\n---------------------\nNe uromorphic Ising Solver with Signed Spiking Neuron and Interleaving Simula ted Annealing for Large-scale Traveling Salesman Problem\n\nThe traveling salesman problem (TSP) is a fundamental combinatorial optimization problem with significant importance in various commercial and industrial domains. Numerous approaches have been proposed to address the TSP, ranging from a dvanced algorithmic heuristics to specialized hardware architect...\n\n\nS eongsik Park (Korea Institute of Science and Technology) and Jongkil Park (KIST)\n---------------------\nPHAP: A Pre-analyzed Head-wise Attention Pa ttern for Efficient Sparse Attention in LLM Inference\n\nRecent advancemen ts in large language models (LLMs) have demonstrated powerful capabilities across various application domains. At the same time, their quadratic com putational complexity with respect to input sequence length remains a majo r bottleneck for efficient inference and deployment. To mitig...\n\n\nSeon ghan Kwon, Daeyoung Kim, Hyunjae Jang, Jaewook Kim, YeonJoo Jeong, and Inh o Kim (Korea Institute of Science and Technology); Jong-Kook Kim (Korea Un iversity); Seongsik Park (Korea Institute of Science and Technology); and Jongkil Park (KIST)\n---------------------\nTechnology-oriented DTCO frame work using neural compact modeling and polar level-set clustering\n\nIn th is paper, we present a process-aware Design–Technology Co-Optimization (DT CO) framework that rapidly integrates transistor-level process shifts into circuit-level Power–Performance–Area (PPA) analysis. The approach combine s Neural Compact Models (NCM) with polar level-set clus...\n\n\nYongjeong Lee, Jeonghwan Kim, Jinyoung Lee, Youngbin Lee, JeongYeol Kim, and Jung Yu n Choi (Samsung Electronics co. ltd)\n---------------------\nAn Energy-Eff icient Automated Hardware Generator for Edge BCI Systems\n\nElectroencepha lography (EEG) enables non-invasive monitoring of brain activity, but its high channel count and computationally intensive neural models pose major challenges to realizing energy-efficient edge accelerator hardware for rea l-time brain–computer interface (BCI) systems. This work p...\n\n\nChih-Ch yau Yang, Hao-Ruei Jiang, Chien-Ming Wu, and Chun-Ming Huang (TSRI, NIAR)\ n---------------------\nSpec2Plan: A Robust LLM-Powered Framework for Veri fication Plan Generation and Evaluation\n\nVerification planning is a crit ical but highly time and effort consuming stage in modern hardware design flows, requiring engineers to interpret lengthy and complex specifications to derive comprehensive and high-quality verification plans. Moreover, ma nual plan authoring is an error-prone process t...\n\n\nTing-Wei Chen, Tzu -Wei Tseng, Pei-Yun Yen, Xin-Hong Ou, Yun-Ru Li, Hong-Siang Wu, Jheng-Han Lai, and Yi-Xin Yang (National Taiwan University); Yi-Hang Chen, Gung-Yu P an, and Ming-Hui Hsieh (Synopsys); and Chung-Yang (Ric) Huang (National Ta iwan University)\n---------------------\nSTA Accuracy Validation: A Machin e Learning Approach\n\nStatic Timing Analysis (STA) plays a critical role in the design of high-performance digital integrated circuits, ensuring re liable operation under varying process conditions. This paper introduces a machine learning (ML) based approach to the problem of selecting relevant timing paths for STA accur...\n\n\nRujie Yin (Texas A&M University) and R ui Liu, Bogdan Tutuianu, and Florentin Dartu (Taiwan Semiconductor Manufac turing Company)\n---------------------\nSpiker-LL: An Energy-Efficient FPG A Accelerator Enabling Adaptive Local Learning in Spiking Neural Networks\ n\nDeploying adaptive intelligence at the edge remains challenging due to the high computational and energy cost of training neural models. SNNs off er a promising alternative, but enabling on-device learning requires hardw are–algorithm co-design. This paper presents SpikerLL, an FPGA-based SNNs a...\n\n\nAlessio Caviglia, Filippo Marostica, Alessandro Savino, and Stef ano Di Carlo (Politecnico di Torino)\n---------------------\nBeyond Static Policies: Dynamic-PRAC for Balanced and Efficient Rowhammer Mitigation\n\ nRowhammer attacks repeatedly activate DRAM rows and cause bit flips in ad jacent rows. DDR5 introduced Per-Row Activation Counting (PRAC) to address this, but static thresholds and unnecessary distant-row refreshes limit i ts efficiency. This paper proposes Dynamic-PRAC, which adapts mitigation t hresh...\n\n\nJeonghyun Lee and Minwoo Ahn (Yonsei University), Jisung Par k (POSTECH (Pohang University of Science and Technology)), and Jinkyu Jeon g (Yonsei University)\n---------------------\nGZswap: Mitigating GPU I/O B ottlenecks in Heterogeneous Memory Systems through On-Device Zswap\n\nMode rn GPUs face a memory capacity wall as large-scale workloads outgrow pract ical device-memory limits. Scale-up designs with heterogeneous memory (HBM plus DDR and CXL) offer larger footprints, but under memory oversubscript ion current systems rely on Inter-memory relocation (IMR), which drives hi ...\n\n\nBoyeol Choi, Sanghyun Park, Sanyhyun Hong, and Jungrae Kim (Sungk yunkwan University)\n---------------------\nPRAC-Auto: A Flexible and Effi cient Framework for PRAC-Based RowHammer Mitigation\n\nRowHammer (RH) rema ins a leading security threat in modern DRAM. Industry has standardized Pe r-Row Activation Counting (PRAC) for monitoring and Alert Back-Off (ABO) f or mitigation, but ABO's pulse-only ALERT_n exposes little about which row s are at risk or how far recovery has progressed. Lacking a...\n\n\nSeomgi m Jeong (Sungkyunkwan University); Sunggi Ahn (Sungkyunkwan University, Sa msung Institute of Technology); Saeid Gorgin (SKKU); and Jungrae Kim (Sung kyunkwan University)\n---------------------\nSNN Accelerator Testing via S parse Test Matrices\n\nSpiking neural network (SNN) accelerators offer the promise of energy efficiency and edge computing excellence when compared to traditional neural networks. However, they are vulnerable to faults tha t can cause catastrophic failures in safety-critical applications. Manufac turing defects, process var...\n\n\nOsita Ukwuaba and Cory Merkel (Rochest er Institute of Technology)\n---------------------\nSPEEDY: Single-Step Re inforcement Learning Framework for Efficient Analog Circuit Sizing Optimiz ation\n\nReinforcement learning (RL) has shown to be promising in optimall y solving the analog circuit sizing problem from simulations but often res ults in low sample efficiency and long execution times. We introduce SPEED Y, an actor-critic RL framework that leverages a single-step formulation t o improve sam...\n\n\nChun-Yen Yao, Chun-Yen Wu, Matteo Guarrera, Alberto Sangiovanni-Vincentelli, Pierluigi Nuzzo, and Rikky Muller (University of California, Berkeley)\n---------------------\nHigh Fan-in Dynamic Leakage Suppression Standard Cells for Improved Power, Performance, and Area in Ul tra-low Power Circuits Authors: Suprio Bhattacharya and Benton Highsmith Calhoun\n\nThis brief identifies a linear increase in the Elmore delay wit h fan-in size for Dynamic Leakage Suppression (DLS) logic structures, unli ke quadratic increase for Static CMOS logic. We leverage this property to design high fan-in (HFI) DLS standard cells (stdcells) that improves power , performance, ...\n\n\nSuprio Bhattacharya and Benton Calhoun (University of Virginia)\n---------------------\nLighthouse RL: Sample-Efficient Circ uit Optimization via Strategic Reset Points\n\nIn this paper, we introduce Lighthouse RL, a sample-efficient reinforcement learning (RL) approach fo r analog circuit sizing. Traditional methods lack generalization across di fferent performance targets, while standard RL approaches waste resources exploring unpromising regions. Our method addresses...\n\n\nMustafa Gürsoy , Stefan Uhlich, Ryoga Matsuo, Yağız Gençer, Arun Venkitaraman, Chia-Yu Hs ieh, Andrea Bonetti, and Lorenzo Servadei (Sony AI)\n--------------------- \nSPICEMixer - Netlist-Level Circuit Evolution\n\nWe present SPICEMixer, a genetic algorithm that synthesizes circuits by directly evolving SPICE ne tlists. SPICEMixer operates on individual netlist lines, making it compati ble with arbitrary components and subcircuits and enabling general-purpose genetic operators: crossover, mutation, and pruning, ...\n\n\nStefan Uhli ch (Sony Europe B.V., ZNL Deutschland); Andrea Bonetti, Arun Venkitaraman, and Chia-Yu Hsieh (Sony AI); Yagiz Gencer and Mustafa Emre Gursoy (EPFL); Ryoga Matsuo (Sony Europe B.V., ZNL Deutschland); and Lorenzo Servadei (S ony)\n---------------------\nEtch-ViGen: A Video Generation Model for Etch ing Simulation\n\nWith the scaling down of integrated circuit dimensions a nd the increasing complexity of transistor structures, the role of etching in manufacturing has become increasingly critical. We propose an etching simulation approach based on a video generation model, which models the ev olution of the etching...\n\n\nLi Ding, Zhenjie Yao, Lingfei Wang, Rui Che n, Zhiqiang Li, and ling li (IMECAS)\n---------------------\nReConCHF: ReR AM-based Reconfigurable Architecture for Cryptographic Hash Functions with Software/Hardware Integration\n\nAs cryptographic hash functions (CHFs) c ontinue to grow in complexity and computational demand, researchers have t urned to Processing-in-Memory (PIM) architectures to alleviate the data tr ansfer bottlenecks inherent in traditional computing. However, existing wo rks often focus on accelerating indivi...\n\n\nChing-En Kao (Dept. of Comp uter Science & Information Engineering, Chang Gung University) and Chin-Fu Nien (Dept. of Electronics and Electrical Engineering, National Yang Ming Chiao Tung University)\n---------------------\nTIDE: A Triangular Interac tion-Symmetric Dual-Systolic Engine for Efficient Acceleration of Physics- Inspired Optimization\n\nPhysics-inspired optimization (PIO) provides a un ified framework for modeling structured interactions inspired by principle s from statistical physics, with applications spanning machine learning, o perations research, and VLSI design. Representative models—including Hopfi eld neural networks (HN...\n\n\nChia-Hua Yen (Department of Electronic Eng ineering, National Taipei University of Technology); Chin-Fu Nien (Dept. o f Electronics and Electrical Engineering, National Yang Ming Chiao Tung Un iversity); Ren-Guey Lee (Department of Electronic Engineering, National Ta ipei University of Technology); and Yuan-Ho Chen (National Taiwan Universi ty of Science and Technology)\n---------------------\nTrace and Chase: Emp owering LLMs to Identify the Root Cause of Test Failures in RISC-V SoCs vi a Textualized Waveform\n\nIdentifying the root causes of test failures in hardware designs constitutes a significant time bottleneck during the RISC -V SoC verification. Existing fault localization solutions solely yield un verifiable locations without the causality between faults and failures, an d suffer from the impractical ...\n\n\nYicheng Zhong (Institute of Softwar e, Chinese Academy of Sciences; University of Chinese Academy of Sciences) ; Jingzheng Wu and Xiang Ling (Institute of Software, Chinese Academy of S ciences); Hao Lyu (Institute of Software, Chinese Academy of Sciences; Uni versity of Chinese Academy of Sciences); and Zhiqing Rui, Tianyue Luo, and Chen Zhao (Institute of Software, Chinese Academy of Sciences)\n--------- ------------\nCMP-Aware Dummy-Fill Optimization via Generative Modeling an d Measurement-Calibrated Prediction\n\nConventional rule-based dummy-fill methods satisfy density constraints but do not directly minimize chemical– mechanical polishing (CMP) variation, requiring costly post-layout fixing. We propose a learning-based dummy-fill insertion framework that enables p roactive correction at the design sta...\n\n\nJi-Hye Lee (Computer Science Engineer (CSE) Team, Samsung Electronics); Min-Chul Park (Samsung Electro nics, Device Solution); Yeji Kim (Computer Science Engineer (CSE) Team, Sa msung Electronics); Usuk Chae and Byungchul Shin (Technology Development, Samsung Electronics); Hyunjae Jang (Computer Science Engineer (CSE) Team, Samsung Electronics); JAE HYUN KANG (Technology Development, Samsung Elect ronics); and SeongRyeol Kim, Young-Gu Kim, and Dae Sin Kim (Computer Scien ce Engineer (CSE) Team, Samsung Electronics)\n---------------------\nA Fas t and Accurate Surrogate Model for Clock-Mesh Timing Analysis\n\nClock mes hes are an essential technique in high-performance VLSI systems to minimiz e skew and handle On-Chip Variation (OCV) especially in nanometer technolo gies. However, analyzing meshes is difficult due to reconvergent paths and multi-source drivers. The industrial standard is to use SPICE simula...\n \n\nMuhammad Hadir Khan and Matthew Guthaus (University of California, San ta Cruz)\n---------------------\nAtto-Spinformer: An Energy-efficient Magn eto Electric Spin Orbit Logic-based Compute-in-Memory Transformer Architec ture\n\nTransformers form the foundation of modern natural language proces sing, but their performance is limited by GPU memory bandwidth and high en ergy consumption. In-memory computing (IMC) architectures mitigate data tr ansfer overhead, yet remain constrained by power-hungry interfaces. We pre sent a novel...\n\n\nHasita Veluri and Dilip Vasudevan (Lawrence Berkeley National Laboratory)\n---------------------\nFast and Accurate RRAM Write- and-Verify via Hadamard-Encoded Read and ADC-Energy-Reduced HARP\n\nWe pro pose two circuit-aware write–verify (WV) schemes for resistive-RAM (RRAM)– based analog compute-in-memory (ACiM) that reduce the dominant cost of ana log-to-digital converters (ADCs). Hadamard-Encoded Parallel-Verify (HD-PV) improves readout signal-to-noise ratio through Hadamard-dri...\n\n\nIlhua n Choi (Seoul National University); Jiwon Yoo (Yonsei University); and Yoo na Lee, Yewon Jeong, Jason Lee, and Woo-Seok Choi (Seoul National Universi ty)\n---------------------\nLeak-CIM: A PVT-Robust and Energy-Efficient SR AM-CIM Macro Exploiting Transistor Leakage\n\nWe propose Leak-CIM, a PVT-r obust, low-power SRAM-based analog computing-in-memory macro for edge DNN inference. A voltage-mode MAC exploits subthreshold leakage of off-state t ransistors as ultra-high-resistance pseudo-resistors, suppressing dynamic shoot-through current and enabling rail-to-rail op...\n\n\nHiroto Tagata ( Kyoto University), Hiromitsu Awano (Nagoya University), and Takashi Sato ( Kyoto University)\n---------------------\nGeneralized Structural Bias Anal ysis for Corrupt-and-Correct Logic Locking\n\nCorrupt-and-Correct (CAC) lo gic locking techniques offer strong resilience against Boolean satisfiabil ity (SAT) attacks. However, the additional perturbation and correction cir cuitry can introduce detectable structural artifacts. Existing structural attacks and associated metrics remain narrowly sco...\n\n\nJoseph Madera a nd Kyle Juretus (Villanova University)\n---------------------\nTactician: A Formal Workflow for Discovering Unintended Interactions Among Microarchi tectural Defenses\n\nMicroarchitectural attacks continue to expand, prompt ing designers to combine multiple defenses within the same processor. Yet these defenses are typically evaluated in isolation, raising a key problem : when integrated, do they still uphold their security guarantees? To addr ess this, we need a syste...\n\n\nKartik Ramkrishnan, Stephen McCamant, Pe n Yew, and Antonia Zhai (University of Minnesota)\n---------------------\n A 1.31 TOPS/W CGRA Hardware with SIMD and Programmable Memory Address Gene ration Unit for Edge AI\n\nCoarse-Grained Reconfigurable Arrays (CGRA) off ers a balance between a processor's flexibility and a domain-specific acce lerator's high energy efficiency. However, conventional CGRAs typically em ploy some of its Processing Elements (PEs) to compute the addresses for me mory access, resulting in lower...\n\n\nRakshith Harish and Vishnu Nambiar (Institute of Microelectronics, Agency for Science, Technology and Resear ch); Yuntian Liu (School of Electrical and Electronic Engineering, Nanyang Technological University); Yi Sheng Chong (Institute of Microelectronics, Agency for Science, Technology and Research); Wang Ling Goh (School of El ectrical and Electronic Engineering, Nanyang Technological University); an d Rahul Dutta and Anh Tuan Do (Institute of Microelectronics, Agency for S cience, Technology and Research)\n---------------------\nTerastal: Layer-V ariant-based Scheduling for Real-Time Multi-DNN Workloads on Heterogeneous Accelerators\n\nHeterogeneous DNN accelerators map layers in real-time mu lti-DNN workloads to preferred accelerators to minimize latency. However, under skewed workloads, cross-accelerator layer latency difference causes deadline misses. We introduce layer variants, customized layer implementat ions to reduce latenc...\n\n\nSing-Yao Wu, Fengshuo Song, and Eli Bozorgza deh (University of California, Irvine)\n---------------------\nO-RRP: Opti cal Proximity Correction Runtime and Resource Prediction using Machine Lea rning\n\nGrowth of compute resource demand in Optical Proximity Correction (OPC) is driving the adoption of cloud-based workflows, making accurate p rediction of runtime and memory usage crucial to optimize resource allocat ion and scheduling. This paper presents a machine learning-based method fo r predicting ...\n\n\nNeha Sharma, Wyatt Clarke, Dallas Lea, Lei Zhuang, J eonghee Kim, Harsha Krishnareddy, Edward Seabolt, Vandana Mukherjee, and G i-Joon Nam (IBM Research)\n---------------------\nLSTM-Based Performance M odeling for Enhanced Peak Memory Prediction in Layout Versus Schematic Ver ification Tools\n\nPerformance modeling of software tools is crucial for o ptimizing resources and costs, yet precise predictions are challenging due to vast configuration spaces and limited data. While machine learning off ers solutions, it demands extensive data collection. This paper presents a novel methodology usin...\n\n\nNorhan Abdelhafez, Ahmed Hosny, Mohamed Ab ouelyazid, Samar Abd El-Hady, Wael ElManhawy, and Samy Nada (Siemens Digit al Industries Software)\n\nTrack: Student END:VEVENT END:VCALENDAR