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DTSTAMP:20260730T152642Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260729T150000
DTEND;TZID=America/Los_Angeles:20260729T160000
UID:dac_DAC 2026_sess296_ENGPRES436@linklings.com
SUMMARY:Crosstalk Effect prediction and optimization for Detail Routing us
 ing CNN models  and Reinforcement Learning Flow Framework
DESCRIPTION:Loknath Moogi, Mohit Gupta, and Ayush Khare (Cadence Design Sy
 stems, Inc.)\n\nWith the increasing complexity of high-performance VLSI de
 signs at advanced technology nodes below 2 nm, crosstalk-induced signal in
 tegrity and timing violations have emerged as major challenges in physical
  implementation flows. Traditional crosstalk analysis is typically perform
 ed after detailed routing, making post-route fixes computationally expensi
 ve and time-consuming, often leading to prolonged design closure cycles. T
 his work proposes a machine learning–driven framework for the early predic
 tion of crosstalk effects prior to detailed routing and guiding Router to 
 prevent crosstalk effect. The approach leverages deep convolutional neural
  networks (CNNs) to extract spatial and physical features and generate a c
 rosstalk hotspot map that accurately identifies crosstalk-critical nets. T
 o further enhance optimization, the CNN-based predictor is integrated with
  a reinforcement learning–based Cadence Cerebrus flow to guide routing dec
 isions such as net ordering and spacing. Experimental results demonstrate 
 that, after training on 40 Cerebrus regression runs, the proposed model ac
 hieves up to 74% prediction accuracy and delivers up to 15% improvement in
  setup total negative slack (TNS). The trained model is reusable across si
 milar designs within the same technology node, yielding consistent PPA imp
 rovements and significantly reducing overall design turnaround time. The p
 roposed framework enables efficient pre-routing signal integrity analysis,
  minimizes costly post-routing iterations, and improves timing closure, ma
 king it well suited for next-generation VLSI physical design flows.\n\nTop
 ics: AI, Chiplet, Design, EDA, Quantum, Security, Systems\n\n
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