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DTSTAMP:20260730T152642Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260729T150000
DTEND;TZID=America/Los_Angeles:20260729T160000
UID:dac_DAC 2026_sess296_ENGPRES407@linklings.com
SUMMARY:Attacking AES-XTS in Simulation: Pre-Silicon Side-Channel Leakage 
 Assessment
DESCRIPTION:Harikrishnan Balagopal (Synopsys), Emrah Karagoz (Advanced Mic
 ro Devices (AMD)), Shailandar Sachdeva and Karan Hiranandani (Synopsys), K
 arthik Gedela and Ferhat Yaman (Advanced Micro Devices (AMD)), Geethu Sath
 ees Babu and Lang Lin (Synopsys), and Amitabh Das and Sourabh Goyal (Advan
 ced Micro Devices (AMD))\n\nThis work presents a pre-silicon side-channel 
 leakage assessment of an open-source AES-XTS hardware implementation at th
 e RTL level. The complete encryption flow is functionally verified, and sw
 itching activity is captured and converted into high-resolution waveform d
 ata for power reconstruction. A Test Vector Leakage Assessment (TVLA) and 
 Correlation Power Analysis (CPA) are applied to identify statistically sig
 nificant leakage across encryption cycles and the key byte disclosures. Re
 sults reveal dominant leakage during early intermediate datapath operation
 s, motivating targeted security refinement. The study demonstrates the eff
 ectiveness of integrating vector-based power reconstruction with systemati
 c leakage evaluation to expose vulnerabilities prior to fabrication, enabl
 ing cost-effective mitigation and improved hardware security robustness.\n
 \nTopics: AI, Chiplet, Design, EDA, Quantum, Security, Systems\n\n
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