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DTSTAMP:20260730T152642Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260729T150000
DTEND;TZID=America/Los_Angeles:20260729T160000
UID:dac_DAC 2026_sess296_ENGPRES399@linklings.com
SUMMARY:Efficient Routing and Connectivity Repair for Large-Scale Hierarch
 ical Metal Networks
DESCRIPTION:Amogh Gupta and Diwesh Pandey (IBM Research)\n\nPower, clock, 
 and tie networks in modern designs form massive, multi-layer, and hierarch
 ically distributed metal connected components with millions of shapes. Acc
 urately modelling and maintaining connectivity for such nets is critical t
 hroughout the physical design flow, yet existing approaches rely on static
  spatial partitioning, leading to poor scalability, excessive runtime, and
  incorrect connectivity artifacts in hierarchical layouts. \nWe present a 
 bottom-up, shape-driven method to construct the smallest possible metal co
 nnectivity subgraphs using dynamic region queries and disjoint-set union s
 tructures. The approach enables scalable, parallel connectivity modelling 
 while preserving synchronization between physical and logical connectivity
 . To handle hierarchical pin and power interactions, we introduce a pin-ac
 cessibility graph that explicitly models reachability and filters redundan
 t guides using a graph-based algorithm. The resulting subgraphs enable ind
 ependent and parallel execution of connectivity repair, tie-net routing, a
 nd traversal operations. Experimental results on production designs demons
 trate up to a 60× runtime reduction with near-linear multi-thread scalabil
 ity. The method is deployed in industrial server and ASIC design flows, en
 abling fast, correct, and scalable connectivity processing for large-scale
  metal networks.\n\nTopics: AI, Chiplet, Design, EDA, Quantum, Security, S
 ystems\n\n
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