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DTSTAMP:20260730T152642Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260729T150000
DTEND;TZID=America/Los_Angeles:20260729T160000
UID:dac_DAC 2026_sess296_ENGPRES384@linklings.com
SUMMARY:Past Present and Future of CDC & RDC Glitches: Improved Glitch Che
 cker (IGC)
DESCRIPTION:Jebin Mohandas, Rakesh Kandula, Sachin Jain, Max Korbel, and P
 ing Lim (Intel)\n\nCDC & RDC verification faces critical challenges where 
 synthesis optimization introduces glitches undetectable during RTL analysi
 s but manifest as silicon failures, significantly impacting Time to Market
 . Improved Glitch Checker is a novel three-stage methodology addressing sy
 nthesis-induced CDC and RDC issues that traditional EDA tools fail to capt
 ure.\n\n    The core problem arises when synthesis tools perform Boolean a
 lgebraic optimizations that maintain logical equivalence but introduce tim
 ing hazards. For example, the expression A & EN may be optimized to A & (~
 A + EN) using distributive laws, which algebraically simplifies (A & ~A) +
  (A & EN) = A & EN. While functionally equivalent, this optimization creat
 es a critical timing vulnerability: when signal A transitions while EN=0, 
 both A and ~A change simultaneously in opposite directions, causing the in
 termediate AND gate (A & ~A) to momentarily glitch before settling to zero
 . This glitch can propagate through the CDC and RDC path, violating metast
 ability requirements and causing silicon failures that are impossible to d
 etect during RTL-level CDC and RDC analysis.\n\n    Our three-stage soluti
 on employs: (1) Netlist Cone Extraction for targeted combinational logic, 
 (2) Formal glitch analysis using Z3 satisfiability solving, and (3) Don't-
 Touch cell integration preventing synthesis optimization of critical CDC p
 aths. Enablement of the solution  demonstrates successful prevention of sy
 nthesis-induced CDC & RDC  violations, reducing months of silicon debug ti
 me.\n\nTopics: AI, Chiplet, Design, EDA, Quantum, Security, Systems\n\n
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