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DTSTAMP:20260730T152642Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260729T150000
DTEND;TZID=America/Los_Angeles:20260729T160000
UID:dac_DAC 2026_sess296_ENGPRES347@linklings.com
SUMMARY:From design to defense: Pioneering Pre-silicon leakage detection f
 or novel ECC crypto core
DESCRIPTION:Prashee Arora (University of Windsor), Harikrishnan Balagopal 
 (Synopsys), Mitra Mirhassani (University of Windsor), and Lang Lin and Nor
 man Chang (Synopsys)\n\nWe present a practical pre-silicon methodology for
  identifying power side-channel leakage in elliptic-curve cryptography (EC
 C) hardware before tape-out. The approach leverages sign-off–quality activ
 ity and power artifacts to expose data-dependent leakage early in the desi
 gn flow. Cryptography-aware stimuli are applied to ECC RTL to generate swi
 tching activity, followed by time-resolved dynamic power estimation and au
 tomated Welch's t-test (TVLA) analysis. The target design is an Elliptic C
 urve Diffie–Hellman (ECDH) core, an ECC-based IP that relies on scalar mul
 tiplication, implemented with a Karatsuba-based field multiplier optimized
  for area–delay efficiency. Initial analysis of the unprotected implementa
 tion reveals clear and repeatable leakage during the first cycle of the de
 sign, corresponding to public key computation. Although ECC is mathematica
 lly robust, complex arithmetic and data-dependent behavior can unintention
 ally reveal sensitive information through physical side channels if not ad
 dressed during implementation. Our goal is to surface such risks using ana
 lysis flows already trusted for power, performance, and area validation.\n
 Beyond pass/fail screening, the methodology localizes dominant leakage con
 tributors in time and logic, enabling targeted mitigation. The flow is ful
 ly scriptable, reuses standard sign-off tools, and integrates naturally in
 to implementation regressions. Although demonstrated on ECC, the method ge
 neralizes to other cryptographic accelerators and security-critical hardwa
 re, providing a scalable path to pre-silicon side-channel hardening.\n\nTo
 pics: AI, Chiplet, Design, EDA, Quantum, Security, Systems\n\n
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