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BEGIN:VEVENT
DTSTAMP:20260730T152642Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260729T150000
DTEND;TZID=America/Los_Angeles:20260729T160000
UID:dac_DAC 2026_sess296_ENGPRES338@linklings.com
SUMMARY:Hunting RTL Glitches Before They Burn Power: A Practical RTL Succe
 ss Story
DESCRIPTION:Xiaobing Tang (Iluvatar); Zhongming Hou (Keysight Technologies
 ); and Ling Sun, Shixuan Que, Fengyu Xiao, and Wanyan Ji (Iluvatar)\n\nGli
 tch power is the next major optimization frontier. It could cost up to 25%
  of total dynamic power. It is too late and hard to do algorithms or archi
 tecture change in P&R stage. So, it is important to identify such risk and
  optimize the design in RTL stage.\nIn this paper, we propose a new data d
 riven glitch methodology to analyze glitch power in RTL stage. The delay a
 ware glitch propagation is faster and easy to setup compared with other me
 thodology. With the glitch source report the designers can identify the hi
 ghest-impact source and optimize their design to minimize the glitch power
 .\n\nTopics: AI, Chiplet, Design, EDA, Quantum, Security, Systems\n\n
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