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DTSTAMP:20260730T152642Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260729T150000
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UID:dac_DAC 2026_sess296_ENGPRES314@linklings.com
SUMMARY:Lint-Free: A Generative AI Approach to Large Scale Autonomous RTL-
 Lint Correction
DESCRIPTION:Nirmit Jallawar, Mark Mendoza, Samantak Gangopadhyay, Shubham 
 Kumar, Siddharth Bhargav, Yiran Li, Sriram Muthukumar, Kaushal Gandhi, and
  Olivia Wu (Meta)\n\nThe increasing complexity and scale of modern ASIC de
 signs have made RTL linting a critical yet challenging aspect of the hardw
 are development process. Traditional manual linting workflows are slow, er
 ror-prone, and often overwhelmed by the sheer volume of warnings and error
 s generated by industry-standard tools. This bottleneck not only delays de
 sign cycles but also forces teams into undesirable tradeoffs between speed
  and code quality.\nIn this work, we present a novel, fully automated RTL 
 lint remediation platform that leverages codemod technology—previously suc
 cessful in software engineering—and adapts it for hardware design. Our sys
 tem proactively scans RTL codebases using nightly runs of industry-standar
 d lint tools, applies context-aware automated fixes, and validates each ch
 ange through rigorous RTL lint and design verification (DV) workflows. Dis
 ruptive or faulty changes are automatically triaged, while human-in-the-lo
 op review ensures correctness and maintains expert oversight.\nBy automati
 ng repetitive error correction and integrating robust validation, our solu
 tion enables ASIC engineers to focus on high-value design tasks, significa
 ntly improving both efficiency and code quality.\nThis work represents a s
 tep-change in RTL design automation, bridging the gap between software and
  hardware codemod practices, and offers a scalable, adaptive, and reliable
  framework for next-generation ASIC development.\n\nTopics: AI, Chiplet, D
 esign, EDA, Quantum, Security, Systems\n\n
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