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DTSTAMP:20260730T152642Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260729T150000
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UID:dac_DAC 2026_sess296_ENGPRES224@linklings.com
SUMMARY:Automated System for FPGA-Based SoC Prototyping
DESCRIPTION:Stefano Cumia and Andrea Concil (STMicroelectronics)\n\nDesign
 ing System-on-Chips (SoCs) requires a well-organized development process. 
 Pre-silicon validation/verification plays a crucial role; it can be perfor
 med in various ways. Here, simulation and prototyping are addressed. This 
 presentation focuses on digital devices. Therefore, FPGA-based prototyping
  fits perfectly. SoC development requires significant time for RTL coding 
 and IP integration. The design evolves daily. Continuous simulations are l
 aunched, and prototyping must keep pace. Hence, constant realignment betwe
 en the two environments is necessary. The FPGA scenario differs slightly f
 rom the simulation one: some blocks must be replaced (memories, PLLs and o
 thers) when switching from one domain to another. This replacement essenti
 ally involves managing and modifying lists of source code files (Verilog, 
 SystemVerilog and VHDL) used for simulation and FPGA synthesis. Given the 
 complexity of modern designs, manual handling could lead to human mistakes
 . This presentation describes a system, based on Python scripts, for the a
 utomatic transition from simulation to prototyping (and back).\n\nTopics: 
 AI, Chiplet, Design, EDA, Quantum, Security, Systems\n\n
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