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BEGIN:VEVENT
DTSTAMP:20260730T152642Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260729T150000
DTEND;TZID=America/Los_Angeles:20260729T160000
UID:dac_DAC 2026_sess296_ENGPRES217@linklings.com
SUMMARY:Screening Analog Anomality for Security Vulnerability in Digitally
  Verified Crypto Cores
DESCRIPTION:Satoshi Kubota (Kobe University), Kazuki Monta (Secafy), Lih-J
 en Hou and YuLing Lin (Siemens), and Makoto Nagata (Kobe University)\n\nWh
 ile cryptographic modules are digitally verified for logical correctness, 
 they remain susceptible to physical side-channel attacks (SCA). This paper
  proposes a verification flow to determine whether in-depth analog verific
 ation is required for digitally verified cores by identifying security vul
 nerabilities rooted in analog anomalies. By leveraging efficient variation
 -aware analysis flamework, we achieve fast exploration of Points of Intere
 st (PoI) at the transistor level. It was proven that when we heuristically
  select analog quantities such as delay time and charge consumption among 
 the digital paths of secret information within a crypto core, the outliers
  appeared in their statistical distributions and requested further analog 
 investigation. The effectiveness was demonstrated among 17 S-boxes in AES-
 128 bit core, including a particular one embedded with a Hardware Trojan (
 HT). Our statistical logic successfully flagged one unintentionally anomal
 ous S-box and also another intentionally HT-embedded one as the PoI candid
 ates for detailed analog verification. Subsequent Correlation Power Analys
 is (CPA) confirmed that these flagged PoIs revealed secret keys significan
 tly faster than standard S-boxes. The proposed flow achieves signoff accur
 acy 10-1000x faster than brute-force SPICE simulations. This approach empo
 wers designers to systematically  and efficiently introduce analog verific
 ation processes for digital security modules.\n\nTopics: AI, Chiplet, Desi
 gn, EDA, Quantum, Security, Systems\n\n
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