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BEGIN:VEVENT
DTSTAMP:20260730T152642Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260729T150000
DTEND;TZID=America/Los_Angeles:20260729T160000
UID:dac_DAC 2026_sess296_ENGPRES143@linklings.com
SUMMARY:Scalable, Emulation-Friendly,Co-Simulation Testbench for Exhaustiv
 e RISC-V Cluster Configuration Verification
DESCRIPTION:Bheema Thangavelu, Ken Gildersleeve, E J Hannah, and Pravin Ta
 vagad (Tenstorrent)\n\nModern RISC-V CPU clusters are delivered as highly 
 parameterized design families, where variations in core count, microarchit
 ecture, cache hierarchy, interconnect fabric, and system IP produce hundre
 ds or thousands of legal RTL configurations. Verifying only a small number
  of representative configurations is insufficient, as functional and memor
 y-model bugs may manifest only under specific parameter combinations. This
  paper presents a configuration-oriented, emulation-friendly co-simulation
  Testbench framework paired with a JSON-driven RTL generation flow that en
 ables scalable verification across large RISC-V configuration spaces using
  a single reusable testbench. This Testbench flow integrates RISC-V archit
 ectural checking, a memory consistency model interface, and a C++ based ve
 rification methodology including instruction-accurate co-simulation with I
 SS and RVWMO memory-model validation, all while remaining design-agnostic 
 with respect to core microarchitecture and cluster composition through a c
 ompanion script, gen_rtl_top.py, which consumes JSON configuration descrip
 tions to automatically synthesize consistent cluster top-level RTL for eac
 h configuration of cores, clusters, shared cache, and system IP. The same 
 verification environment runs unmodified across Hardware simulation, hardw
 are emulation,early Software bring up on emulation and open-source tools s
 uch as Verilator, enabling efficient, vendor-independent configuration-spa
 ce exploration and high-throughput verification of complex RISC-V cluster 
 families.\n\nTopics: AI, Chiplet, Design, EDA, Quantum, Security, Systems\
 n\n
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