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BEGIN:VEVENT
DTSTAMP:20260730T152642Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260729T150000
DTEND;TZID=America/Los_Angeles:20260729T160000
UID:dac_DAC 2026_sess296_ENGPRES033@linklings.com
SUMMARY:Intelligent Clock Domain Crossing: Activity-Aware Synchronization 
 for Low-Power SoCs
DESCRIPTION:Aradhana Kumari (STMicroelectronics)\n\nModern SoCs integrate 
 multiple asynchronous clock domains, making Clock Domain Crossing (CDC) fo
 r control signals a critical design challenge. Conventional n-flop synchro
 nizers, though robust, remain continuously clocked, causing significant dy
 namic power dissipation and area overhead—especially when control signals 
 toggle sparsely. This paper introduces an activity-aware CDC architecture 
 that intelligently gates synchronizer clocks, activating only during signa
 l transitions. By grouping control signals into synchronizer banks and emp
 loying transition detection, the proposed method drastically reduces idle 
 power while preserving CDC fidelity. As demonstrated in 28 nm FDSOI at 600
  MHz, the architecture achieves up to 90% dynamic power savings for low to
 ggle rates and over 30% area reduction compared to traditional synchronize
 r designs. Results highlight scalability for large SoCs with thousands of 
 control signals, delivering exceptional energy efficiency without function
 al compromise. Fully digital and technology-agnostic, this solution enable
 s automated integration into RTL flows, making it ideal for next-generatio
 n low-power, high-performance systems.\n\nTopics: AI, Chiplet, Design, EDA
 , Quantum, Security, Systems\n\n
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