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DTSTAMP:20260730T152642Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260729T150000
DTEND;TZID=America/Los_Angeles:20260729T160000
UID:dac_DAC 2026_sess296_ENGPRES027@linklings.com
SUMMARY:A Rule-Aware Layout Conversion Framework for Back-End Physical Des
 ign
DESCRIPTION:Jaeeun Kim (Samsung); Juhyun Kang (Cadence Design Systems, Inc
 .); Hyunchul Hwang (Samsung Electronics); and Gwanghoon Yun and WoongSik J
 ung (Cadence Design Systems, Inc.)\n\nAs technology nodes continue to scal
 e, DTCO (Design-Technology Co-Optimization) increasingly requires layout t
 eams to evaluate multiple architectural options early in the design cycle—
 especially in standard cells and SRAM periphery, where small structural ch
 anges can significantly affect area, performance, and DRC results.\nIn rea
 lity, layout implementation has not kept pace with this demand. Even modes
 t architectural updates often invalidate existing layouts, forcing enginee
 rs to repeatedly rework structurally similar designs and slowing down DTCO
  feedback loops.\n\nThis work presents a lightweight, rule-aware layout co
 nversion framework aimed at reducing repetitive layout modification effort
  at the cell- and library-level. Rather than introducing a new design flow
 , the framework focuses on automating common but time-consuming tasks such
  as cell-height migration, layout template regeneration, and structural re
 factoring under updated design rules. Each transformation step is performe
 d in a DRC-conscious manner, helping preserve layout intent and physical c
 onsistency.\n\nExperimental evaluations on standard cell and memory-relate
 d layouts demonstrate significant reductions in layout turnaround time whi
 le maintaining area efficiency and rule compliance comparable to hand-craf
 ted designs. The framework integrates smoothly into existing back-end envi
 ronments with minimal disruption, making it practical for everyday use.\nI
 n the longer term, this structured approach also establishes a solid found
 ation for future AI-assisted layout automation grounded in real layout exp
 ertise and reusable transformation logic.\n\nTopics: AI, Chiplet, Design, 
 EDA, Quantum, Security, Systems\n\n
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