BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20260730T152729Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260729T150000
DTEND;TZID=America/Los_Angeles:20260729T160000
UID:dac_DAC 2026_sess296_ENGPOST458@linklings.com
SUMMARY:New Thermal Analysis Workflow for 3DIC Designs
DESCRIPTION:Subramanian Lalgudi (Siemens); Sadha Parasuraman, Nitish Kumar
 , Nicholas Neal, and Satish Surana (Intel); and Mike Walsh (Siemens)\n\nPo
 wer density and total power are higher in 3DIC designs compared to monolit
 hic system on chip (SoC) designs, making thermal integrity a greater conce
 rn in 3DIC designs. Given the increased risk of thermal issues, thermal an
 alysis must start from the early stages of a design and be progressively r
 efined as the design matures. It is desirable to embed the thermal analysi
 s in the same tool/platform that 3DIC designers use and have an option to 
 import the same thermal design into a CFD tool, which system thermal exper
 ts are familiar with. This facilitates efficient collaboration between ele
 ctronics designers and thermal experts. Traditional thermal analysis workf
 low starts only after the chip design is completed and hence not suitable 
 for 3DIC design needs. This paper proposes a new workflow for thermal anal
 ysis for 3DIC designs leveraging Siemens IC-Packaging solutions and demons
 trate its working on several representative Intel designs and process tech
 nologies.\n\nTopics: AI, Chiplet, Design, EDA, Quantum, Security, Systems\
 n\n
END:VEVENT
END:VCALENDAR