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BEGIN:VEVENT
DTSTAMP:20260730T152727Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260729T150000
DTEND;TZID=America/Los_Angeles:20260729T160000
UID:dac_DAC 2026_sess296_ENGPOST446@linklings.com
SUMMARY:A Scalable Timing Analysis and Closure Methodology for Ultra-Large
  Designs
DESCRIPTION:Avinash Sekar and ABUBAKAR SIDDIK KANCHARA (Qualcomm) and Arvi
 nd NV, Daksh Bakshi, Harivenkadesh Mohanraj, Himanshu Tanwar, Chaya N, and
  Harish G (Cadence Design Systems, Inc.)\n\nUltra‑large digital designs at
  advanced technology nodes now include billions of instances, deep hierarc
 hies, and highly complex clocking and interconnect structures, making trad
 itional flat static timing analysis (STA) increasingly impractical. Timing
  closure cycles have become prohibitively long due to excessive runtime, m
 emory demands, and limited visibility across block boundaries. This work p
 resents a scalable and silicon‑correlated timing analysis and closure meth
 odology tailored for these massive designs. The approach unifies Boundary 
 Model, Context‑Aware Timing, and Advanced Multi‑Input Switching (AMIS) to 
 deliver accurate hierarchical timing without requiring design flattening. 
 Boundary Model preserves interface logic by abstracting internal logic in 
 order to reduce design size, while Context‑Aware Timing ensures that each 
 block's interface timing remains aligned with top‑level requirements, rega
 rdless of differences introduced by independently developed constraints. A
 MIS effectively addresses inherent optimism in single‑input switching by c
 apturing simultaneous switching effects. Combined with Tempus ECO and Cert
 us, the methodology enables fast, localized optimization and predictable c
 onvergence. Applied to a multi‑billion‑instance design across 150+ timing 
 views, the flow demonstrates 3.5×–5× runtime improvement, 50–65% memory re
 duction, and strong correlation with flat STA. This scalable methodology p
 rovides a robust foundation for achieving efficient timing closure in emer
 ging high‑performance systems.\n\nTopics: AI, Chiplet, Design, EDA, Quantu
 m, Security, Systems\n\n
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