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DTSTAMP:20260730T152729Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260729T150000
DTEND;TZID=America/Los_Angeles:20260729T160000
UID:dac_DAC 2026_sess296_ENGPOST444@linklings.com
SUMMARY:Crosstalk Hotspot Map creation at Placement stage using CNN UNET p
 rediction model
DESCRIPTION:Loknath Moogi (Cadence Design Systems, Inc.)\n\nEarly identifi
 cation of crosstalk-affected regions is critical for achieving timing clos
 ure in advanced VLSI designs. This paper presents a framework for the pre-
 routing prediction of coupling-induced timing and signal integrity risks w
 ithin the physical design flow. The proposed method introduces a novel Cou
 pling Capacitance Estimator (CCE) to accurately estimate coupling effects 
 arising from neighboring interconnects.\nThe framework extracts multi-chan
 nel spatial features from the Innovus placement database, including conges
 tion, pin density, timing criticality, routing density, macro blockages, a
 nd coupling characteristics, and feeds them into a CNN-based U-Net archite
 cture to generate high-resolution crosstalk hotspot maps. Owing to its enc
 oder–decoder structure with skip connections, the U-Net model preserves fi
 ne-grained spatial information and enables precise localization of crossta
 lk-sensitive regions in dense layouts.\nExperimental evaluation across mul
 tiple design blocks demonstrates that the generated heatmaps closely corre
 late with post-routing signoff results, indicating strong predictive fidel
 ity. By enabling reliable pre-routing crosstalk analysis, the proposed fra
 mework reduces dependence on costly post-routing iterations and supports i
 mproved timing closure, reduced design turnaround time, and enhanced physi
 cal implementation efficiency, making it well suited for advanced technolo
 gy nodes.\n\nTopics: AI, Chiplet, Design, EDA, Quantum, Security, Systems\
 n\n
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