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DTSTAMP:20260730T152727Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260729T150000
DTEND;TZID=America/Los_Angeles:20260729T160000
UID:dac_DAC 2026_sess296_ENGPOST430@linklings.com
SUMMARY:Reduced Order Modelling (ROM) based Full Chip EMIR signoff
DESCRIPTION:Pradhosh Lakshmi Narasimhan (Synopsys), Akshay Khare (Samsung 
 Electronics), and Vinuja Sridhar and PRATHWIKA KANNAGOLA PRAKASH (Synopsys
 )\n\nElectromigration and IR drop (EMIR) signoff at advanced process nodes
  demands prohibitively large compute resources, often requiring thousands 
 of cores and multi day runtimes for full chip flat analysis. As design siz
 es and scenario counts increase, traditional methodologies fail to scale, 
 limiting coverage and delaying signoff closure. This work presents a scala
 ble Reduced Order Modeling (ROM)–based hierarchical EMIR signoff flow that
  delivers flat analysis level accuracy with dramatic improvements in turna
 round time and memory efficiency.\nThe proposed flow abstracts each block 
 into a scenario aware ROM containing geometry, circuit representation, dem
 and currents, and decap models. These ROMs are generated once at block lev
 el and reused across all top level instantiations, enabling flexible confi
 guration of detail granularity per instance. In full chip analysis, ROM co
 nsumption significantly reduces simulation complexity while preserving IR 
 drop fidelity.\nResults on a production scale GPU design demonstrate 86% r
 untime reduction (30.4 hrs → 4.21 hrs) and 52% lower memory usage, using i
 dentical core counts. IR drop correlation remains exceptionally strong: 99
 .9% of instances within ±10 mV, with peak delta under 15 mV across vectorl
 ess and DFT vector scenarios. These results establish ROM based EMIR analy
 sis as a practical, high accuracy alternative to flat signoff, enabling br
 oader scenario coverage, faster iteration, and scalable deployment across 
 SoC design teams.\n\nTopics: AI, Chiplet, Design, EDA, Quantum, Security, 
 Systems\n\n
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