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DTSTAMP:20260730T152727Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260729T150000
DTEND;TZID=America/Los_Angeles:20260729T160000
UID:dac_DAC 2026_sess296_ENGPOST426@linklings.com
SUMMARY:Zero‑Glitch Confidence: An End‑to‑End Static, Formal & Simulation 
 Methodology
DESCRIPTION:Anshul Bansal and Gunjan Mamania (Meta), Srinidhi Parshi and S
 uresh Babu Barla (Synopsys), SWETHA KARUSALA (Meta), and suresh barla (Syn
 opsys)\n\nGlitches in synthesized netlists continue to pose significant ri
 sks to functional correctness, especially in deeply optimized, high‑perfor
 mance digital designs. While structural glitch analysis provides fast, des
 ign‑wide coverage, it alone cannot fully capture the functional conditions
  under which hazards become observable. Conversely, formal verification an
 d dynamic simulation each offer deeper semantic insight but suffer from sc
 alability or stimulus limitations. This work presents a unified methodolog
 y that combines static/structural glitch detection with formal and simulat
 ion-based verification to deliver end‑to‑end confidence in glitch‑free imp
 lementations.\nWe introduce techniques for cross‑domain correlation, where
  structural analysis first identifies potential hazard sites, which are th
 en refined through formal trace generation or targeted simulation. For exa
 mple, in control-heavy FSM logic, structural + simulation verification ena
 bles exhaustive proof that identified glitch cones cannot propagate to sta
 te elements under any reachable condition. Similarly, in asynchronous FIFO
 , Formal techniques are used to identify glitches in Empty signal. Experim
 ental results show that the combined flow significantly reduces false posi
 tives, improves coverage, and enables practical signoff for glitch vulnera
 bilities in complex SoC blocks.\n\nTopics: AI, Chiplet, Design, EDA, Quant
 um, Security, Systems\n\n
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