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DTSTAMP:20260730T152727Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260729T150000
DTEND;TZID=America/Los_Angeles:20260729T160000
UID:dac_DAC 2026_sess296_ENGPOST405@linklings.com
SUMMARY:Rapid design and deployment of high-radix switch fabric for Scale-
 up and Scale-out AI Systems
DESCRIPTION:Saurabh Gayen (Baya Systems)\n\nNext-generation scale-up and s
 cale-out AI systems require high-radix switches that deliver high bandwidt
 h, low latency, and non-blocking performance while scaling to hundreds of 
 ports. Traditional switch fabrics are typically implemented using large cr
 ossbars, which satisfy performance requirements but present significant im
 plementation and physical design (PD) challenges. As port counts increase,
  crossbars become increasingly difficult to develop, floorplan, route, and
  time, and pose fundamental barriers to scaling across chiplets for contin
 ued growth in number of ports.\n\nThis work presents NeuraScale, a scalabl
 e, non-blocking switch fabric architecture designed to address these chall
 enges. The fabric employs a hybrid topology that combines the scalability 
 and PD regularity of mesh-based structures with Clos-style connectivity to
  provide system-level non-blocking behavior. The architecture is construct
 ed from repeatable, PD-friendly tiles that can be replicated to build larg
 e fabrics, including across chiplets, enabling rapid design iteration and 
 deployment.\n\nPerformance evaluation of a 128×800G (102.4 Tb/s) AI switch
  under permutation traffic demonstrates 100% peak throughput with flat lat
 ency, while a conventional mesh saturates at 73% throughput with sharply i
 ncreasing latency. This approach enables practical realization of high-rad
 ix, chiplet-ready AI switches for large-scale AI systems.\n\nTopics: AI, C
 hiplet, Design, EDA, Quantum, Security, Systems\n\n
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