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DTSTAMP:20260730T152727Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260729T150000
DTEND;TZID=America/Los_Angeles:20260729T160000
UID:dac_DAC 2026_sess296_ENGPOST403@linklings.com
SUMMARY:Free hand routing- sketch to layout
DESCRIPTION:Diwesh Pandey, Jayant Singh, Surya Siriki, Alaparthi Sai, and 
 Kiruthika Balachandran (IBM Research)\n\nDespite significant advances in r
 outing automation, manual routing remains a critical and time-consuming ta
 sk in modern VLSI design, particularly for small layout experiments, debug
 ging, and structured or analog routing. This paper introduces Free Hand Ro
 uting, a new paradigm that enables designers to sketch routing topologies 
 directly using free-form drawings, while automatically transforming these 
 sketches into technology-correct, DRC-clean, and manufacturable layouts.\n
 The proposed approach extracts shapes and connectivity from free-hand draw
 ings, maps them to technology-specific width and spacing rules, and applie
 s a connectivity-aware geometric transformation flow. This flow aligns sha
 pes to legal routing tracks, restores connectivity using a graph-driven sh
 ape extension mechanism, and inserts vias to ensure full 3D connectivity a
 cross metal layers. The final layout is exported using a structured, tool-
 agnostic JSON representation, enabling seamless integration with existing 
 physical design tool chains.\nIntegrated into an industrial physical desig
 n environment, the approach has been used to generate hundreds of test lay
 outs, reducing per-case effort from hours of manual coding to seconds of i
 ntuitive sketching.\n\nTopics: AI, Chiplet, Design, EDA, Quantum, Security
 , Systems\n\n
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