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BEGIN:VEVENT
DTSTAMP:20260730T152729Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260729T150000
DTEND;TZID=America/Los_Angeles:20260729T160000
UID:dac_DAC 2026_sess296_ENGPOST393@linklings.com
SUMMARY:ENHANCED AUTOMATION FOR GENERATING LOGIC-OPTIMIZATION ECOs (EAGLE)
  IN SIGNOFF
DESCRIPTION:Bhukya Sardar, Ketavanya Dubakula, Satish Sethuraman, Anantakr
 ishnan NS, and Naveen Bishnoi (Intel)\n\nModern high-performance digital c
 ircuits face significant challenges in achieving optimal timing closure du
 e to the complexity of designs with millions of transistors. While APR too
 ls provide sophisticated optimization capabilities, they often compromise 
 on local optimizations due to global constraints, tool limitations, and PP
 A trade-offs. Non-optimized structures residing on critical paths directly
  impact on the achievable operating frequency, creating performance bottle
 necks. During the ECO phase, setup violating paths undergo re-ordering, cr
 eating opportunities for logic optimization. The positive slack paths, whi
 ch were not optimization targets during synthesis, become exposed during E
 COs and offer greater potential for logic optimization to achieve timing t
 argets. However, current solutions suffer from lack of Primetime compatibi
 lity and absence of direct APR tool integration, necessitating manual inte
 rvention that extends design closure timelines. EAGLE overcomes these cons
 traints through a comprehensive Primetime-integrated framework that levera
 ges ECO-phase optimization opportunities and delivers APR tool-compatible 
 ECOs directly.\n\nTopics: AI, Chiplet, Design, EDA, Quantum, Security, Sys
 tems\n\n
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