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DTSTAMP:20260730T152727Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260729T150000
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UID:dac_DAC 2026_sess296_ENGPOST352@linklings.com
SUMMARY:AI-Accelerated Signoff Verification and Glitch Analysis for Single
  and Multibit Level Shifters
DESCRIPTION:Raghu BM and Hareharan Nagarajan (Intel) and Ajaj Ansari and J
 ayne Alexander (Siemens)\n\nLevel shifters are critical for reliable cross
 -voltage domain communication: their failure risks the integrity of the ci
 rcuit, excessive power dissipation, and damage to components. Extensive ve
 rification is required to mitigate their susceptibility to device variabil
 ity and multiple failure mechanisms. Traditional brute-force Monte Carlo a
 nalysis is infeasible for evaluating all failure modes across large corner
  sets at advanced nodes, making accurate, timely verification challenging.
 \n\nThis paper introduces an AI-powered, high-throughput batch flow for fa
 st, accurate signoff verification of single and multibit level shifter cel
 ls. Adaptive AI performs rapid identification of worst-case corners, which
  are then verified with AI-powered, brute-force accurate high-sigma techno
 logy. This precision deployment optimizes runtime and resources by running
  high-sigma verification only when necessary.\n\nThe proposed methodology 
 demonstrates significant improvements over previous methods. 3σ single-cel
 l validation was 3x faster than traditional brute-force Monte Carlo, and h
 igh-sigma verification precision deployment reduced overall runtime by 10x
  across 256 cells at 6σ. Targeted analysis validated glitch heights in mul
 tibit level shifters at 3σ and 6σ, with precision deployment reducing over
 all runtime by >14x. This AI-driven solution optimizes compute and enginee
 ring resources to provide timely, accurate guidance on reduced verificatio
 n timelines, ensuring full-coverage functional robustness, improved silico
 n quality, and faster time-to-market.\n\nTopics: AI, Chiplet, Design, EDA,
  Quantum, Security, Systems\n\n
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