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DTSTAMP:20260730T152728Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260729T150000
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UID:dac_DAC 2026_sess296_ENGPOST351@linklings.com
SUMMARY:Accelerating Memory Cache Verification with AI-Powered Batch Flow 
 Methodology
DESCRIPTION:Anik Srivastava and Sai Surya Kannan (Qualcomm) and Jayne Alex
 ander (Siemens)\n\nAchieving rigorous 6-6.5σ yield targets in L1 caches an
 d other memory IP components requires extensive high-sigma verification. H
 owever, traditional brute-force Monte Carlo simulations and manually pilot
 ed GUI-based analyses are too slow and inefficient to verify large numbers
  of cells within tight project timelines, limiting analysis scope and comp
 romising critical worst-case corner identification.\n\nThis paper introduc
 es an innovative AI-powered batch flow that automates and significantly ac
 celerates high-sigma memory cache verification, ensuring accurate, full-co
 verage analysis across all cells and components. The proposed methodology 
 leverages adaptive AI to rapidly identify worst-case corners and eliminate
 s unnecessary high-sigma runs by only deploying brute-force accurate verif
 ication on the identified critical corners. \n\nIn an example testcase, th
 is AI-powered batch flow achieved full-coverage verification across 726 ne
 tlists in 38 hours and 20 minutes, averaging 2,514 simulations per job, re
 presenting an average 3.25x runtime speedup and 2.4x simulation speedup pe
 r job over the previous GUI-based method. Enhanced modeling and yield solv
 er algorithms also contributed to reducing per-job simulations, and the fl
 ow automation and parallelization reduced engineering effort and overall r
 untime, making full coverage verification feasible within production timel
 ines and improving disk space management. This scalable, AI-driven flow pr
 ovides a fast, accurate, and comprehensive solution for memory IP validati
 on challenges.\n\nTopics: AI, Chiplet, Design, EDA, Quantum, Security, Sys
 tems\n\n
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