BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20260730T152728Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260729T150000
DTEND;TZID=America/Los_Angeles:20260729T160000
UID:dac_DAC 2026_sess296_ENGPOST342@linklings.com
SUMMARY:Dynamic CDC Verification using SVA for Waiver Review
DESCRIPTION:Megha Hansaliya and Sushovan Kunti (Google)\n\nAsynchronous cl
 ock domains in modern SoC designs present critical verification challenges
 , as Clock Domain Crossing (CDC) issues remain the second most common caus
 e of silicon re-spins. While static CDC ensures structural synchronization
 , it relies on manual constraints and waivers that may be inaccurate or hi
 de functional bugs. Furthermore, formal analysis often leaves properties "
 partially proven" due to computational complexity.\n\nThis paper proposes 
 a closed-loop methodology to validate these "design intent" assumptions dy
 namically. The flow begins by running structural CDC and filtering results
  to identify waived paths. These waivers—including those translated from T
 CL to constraint formats—are converted into protocol-aware SystemVerilog A
 ssertions (SVA). By integrating these SVAs into dynamic simulation, engine
 ers can stress-test protocols like data-hold and glitch protection.\n\nIf 
 simulations pass, waiver validity is confirmed for sign-off; failures trig
 ger design or constraint refinement. This methodology is a "MUST" for SoC 
 design, uncovering corner-case bugs unreachable via manual reviews. Key ad
 vantages include significantly reduced Turnaround Time (TAT) and high-qual
 ity sign-off guaranteed by measurable assertion coverage.\n\nTopics: AI, C
 hiplet, Design, EDA, Quantum, Security, Systems\n\n
END:VEVENT
END:VCALENDAR