BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20260730T152729Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260729T150000
DTEND;TZID=America/Los_Angeles:20260729T160000
UID:dac_DAC 2026_sess296_ENGPOST332@linklings.com
SUMMARY:Early DEF-Based Hierarchical Power Grid Shorts Analysis
DESCRIPTION:Sanghmitra Jha and Greg Ford (Marvell)\n\nHierarchical power g
 rid shorts represent a critical challenge in modern chip design, typically
  discovered late in the schedule during physical verification and LVS anal
 ysis at integration, causing significant delays and expensive fixes near t
 apeout. This work presents an innovative DEF-based methodology to detect p
 ower grid shorts early in the PNR flow with exact coordinate reporting. Th
 e approach analyzes power and ground net shapes to identify unintended col
 lisions between different net types, particularly for multi-voltage domain
  crossings. By processing DEF data from individual PNR blocks in the conte
 xt of their hierarchical placement, the methodology enables shorts identif
 ication in hours rather than days. This system integrated at the floorplan
  level of the PNR implementation flow significantly reduces physical verif
 ication churn, eliminates weeks of LVS iteration, and improves design sche
 dule predictability while providing precise location information for rapid
  resolution.\n\nTopics: AI, Chiplet, Design, EDA, Quantum, Security, Syste
 ms\n\n
END:VEVENT
END:VCALENDAR