BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20260730T152728Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260729T150000
DTEND;TZID=America/Los_Angeles:20260729T160000
UID:dac_DAC 2026_sess296_ENGPOST331@linklings.com
SUMMARY:Timing Aware Power Integrity enhancement in Performance Core Archi
 tectures through Advanced Custom Global PG-Fill Techniques
DESCRIPTION:Joel Joy, Sudhakar Maruthi, Joshy Mathew, Madhur Jagota, and A
 nand Rajagopalan (MediaTek USA)\n\nPower integrity in high-performance com
 puting systems is crucial for ensuring reliable and efficient operation. W
 ith each generation, high-performance CPU cores are significantly increasi
 ng in area and power to meet compute needs. Power integrity has become a c
 ritical factor in CPU silicon performance, as CPUs are starting to throttl
 e before achieving the STA frequency due to power budgets and thermal limi
 tations. General-purpose CPUs used in various product segments often face 
 coverage issues, making it challenging to sign off on power integrity with
  a limited number of vectors. Therefore, a global solution is needed to en
 sure robust electrical performance and reliability.\n\nGlobal PG-Fill prov
 ides reinforcement to the existing Power Delivery Network (PDN), improving
  PDN resistance, reducing voltage drops, and minimizing electromagnetic in
 terference.\n\nIn this paper, we discuss how we utilized opportunistic tra
 ck-based PG-Fill using Cadence Pegasus and optimally integrated it with th
 e existing PDN to enhance power integrity while addressing challenges such
  as runtime and timing degradation. We propose our custom solution by opti
 mally controlling STAMP lengths, adding additional PG VIAs, and improving 
 the overall effective resistance of the design. We also address key challe
 nges, such as timing degradation caused by PG-Fill, and how our custom sol
 ution helped to minimize these issues.\n\nUsing the proposed custom soluti
 on, we achieved an improvement of approximately 20% in overall PDN resista
 nce and 88% cleanup in overall dynamic IR violations, resulting in a more 
 robust design. All of this was achieved without introducing any additional
  DRC violations.\n\nTopics: AI, Chiplet, Design, EDA, Quantum, Security, S
 ystems\n\n
END:VEVENT
END:VCALENDAR