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BEGIN:VEVENT
DTSTAMP:20260730T152727Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260729T150000
DTEND;TZID=America/Los_Angeles:20260729T160000
UID:dac_DAC 2026_sess296_ENGPOST307@linklings.com
SUMMARY:SLC-Based Real-Time Traffic Buffering with DRAM Row-Aware Write Ba
 ck
DESCRIPTION:Soojin Park (Samsung Electronics)\n\nReal-time (RT) traffic in
  modern SoCs is often assigned the highest priority to meet strict latency
  requirements during traffic bursts. However, aggressively servicing urgen
 t RT requests forces immediate DRAM access, breaking row locality and incr
 easing read/write direction switching. This degrades DRAM efficiency and c
 auses non-real-time (NRT) traffic to be repeatedly delayed under shared re
 source contention, reducing overall system performance.\n\nWe propose an S
 LC-based Real-Time write buffering mechanism that decouples RT urgency fro
 m DRAM scheduling. RT write requests are absorbed by SLC(System-level-cach
 e) and acknowledged immediately preserving bounded RT latency while allowi
 ng RT traffic priority to be safely lowered. \nWhen draining RT data buffe
 red in the SLC to DRAM, deferred writebacks are issued only when the DRAM 
 path is less congested. To further improve memory efficiency, the SLC grou
 ps writebacks targeting the same DRAM row and issue them consecutively. A 
 small DRAM Row-Aware Buffer (DRAB) tracks unique row addresses of buffered
  RT writes and enables row-grouped writeback generation.\n\nThis approach 
 reduces priority-driven interference, improves DRAM scheduling efficiency,
  and allows NRT traffic to make steady forward progress with minimal archi
 tectural changes.\n\nTopics: AI, Chiplet, Design, EDA, Quantum, Security, 
 Systems\n\n
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