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DTSTAMP:20260730T152727Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260729T150000
DTEND;TZID=America/Los_Angeles:20260729T160000
UID:dac_DAC 2026_sess296_ENGPOST299@linklings.com
SUMMARY:Vmin Reliability through Critical Path-Aware PDN Analysis
DESCRIPTION:Mohit Jain (Qualcomm), Roshan Roy (Synopsys), and Athanasios G
 karas (Qualcomm)\n\nEnsuring reliable chip operation at minimum voltage (V
 min) demands robust analysis of timing, thermal, and power delivery networ
 ks (PDN). Traditional transient analysis methods are computationally inten
 sive and impractical for evaluating PDN across all critical path scenarios
 . This work introduces the Path-aware SigmaAV (PSAV) methodology, which le
 verages Sigma technology in RedHawk-SC to efficiently simulate worst-case 
 voltage drops. Critical paths extracted via PrimeTime are analyzed using a
 ggressor voltage impact data, enabling realistic scenario generation witho
 ut exhaustive transient simulations. The PSAV flow back-annotates worst-ca
 se drops into PrimeTime for slack analysis, guiding targeted PDN reinforce
 ment. Applied to a 100M-instance design, PSAV simulated 1.9M path segments
  in 6 hours using 127 workers, outperforming traditional VCD-based methods
  in both coverage and accuracy. Over 90% of critical path instances were b
 etter analyzed in a single PSAV run, revealing slack violations missed by 
 conventional techniques. Future enhancements aim to refine aggressor selec
 tion for broader coverage. PSAV presents a scalable, performance-efficient
  solution for Vmin reliability assurance.\n\nTopics: AI, Chiplet, Design, 
 EDA, Quantum, Security, Systems\n\n
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