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DTSTART:19700308T020000
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DTSTAMP:20260730T152730Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260729T150000
DTEND;TZID=America/Los_Angeles:20260729T160000
UID:dac_DAC 2026_sess296_ENGPOST292@linklings.com
SUMMARY:Real-Time Local Layout Effects Analysis for Advanced Design Optimi
 zation
DESCRIPTION:Ahmed Saleh (Siemens); Woonggyu Lee, Taehyung Lee, Jongku Kang
 , and Jooyoung Song (Samsung Electronics); and Mohamed Alimam (Siemens)\n\
 nEnsuring accurate extraction of Local Layout Effects (LLE) parameters in 
 LVS rule decks is critical for maintaining electrical yield as technology 
 nodes scale below 5nm. While LLE parameter extraction is essential for fou
 ndry process integrity, the key design challenge is translating these phys
 ical parameters into electrical impacts specifically threshold voltage (Vt
 h) and mobility (u0) variations before costly layout simulation. A new Rea
 l-Time LLE design-aware methodology is introduced that processes extracted
  LLE parameters with foundry-provided equations to compute per-device elec
 trical impacts in real-time. Our approach detects physically placed neighb
 oring cells near target devices and translates LLE physical parameters int
 o electrical parameters (Vth/u0), enabling immediate performance assessmen
 t. This methodology addresses two critical design scenarios: First, layout
 -integrated visualization after LVS runs enables designers to easily ident
 ify, review, and measure how LLE parameters affect device performance, eff
 iciently guiding layout modifications for improved yield. Second, schemati
 c designers gain insights about LLE parameter effects using reference layo
 uts before physical design begins, allowing them to mimic optimal layout b
 ehavior during early design stages. Deployed across multiple technology no
 des, Real-Time LLE analyzes millions of devices in hours versus days, fund
 amentally transforming the design flow by enabling early detection and mit
 igation of LLE-induced performance variations.\n\nTopics: AI, Chiplet, Des
 ign, EDA, Quantum, Security, Systems\n\n
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