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DTSTAMP:20260730T152727Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260729T150000
DTEND;TZID=America/Los_Angeles:20260729T160000
UID:dac_DAC 2026_sess296_ENGPOST282@linklings.com
SUMMARY:Optimizing GPU Clock Power: Exploring Register Array Folding and I
 ts Trade-Offs
DESCRIPTION:Deepayan Dasgupta (Samsung Electronics)\n\nRegister arrays in 
 GPU design consume significant power due to clock tree complexity and addr
 essing logic. Analysis of a key GPU gaming workload revealed that a group 
 of register arrays account for 10.3% of the total sub-block power, making 
 them a prime target for optimization. \n\nClock power can be reduced by sh
 rinking entry bit width and/or decreasing array depth or count. However, t
 his can impact performance due to reduced capacity increasing stalls, whic
 h can introduce  backpressure within a design. \n\nAccess pattern analysis
  showed that consecutive arrays are often accessed together, allowing them
  to be folded into fewer, wider arrays, preserving capacity and avoiding p
 erformance loss. This approach, called access pattern-based array folding,
  reduces addressing logic and clock power. An example optimization achieve
 d a 2.75% net power reduction, 0.63% reduction in standard cell area, and 
 13.15% reduction in total ICG count. \n\nThe solution has broad applicabil
 ity across industries, including CPU, AI/ML, networking, and SoC, and prov
 ides a systematic, architecture‑agnostic method for global clock-tree simp
 lification. By leveraging access patterns to optimize register array desig
 n, this novel approach can reduce power consumption while preserving capac
 ity and performance, making it a valuable technique for various designs ac
 ross the industry.\n\nTopics: AI, Chiplet, Design, EDA, Quantum, Security,
  Systems\n\n
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